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參數(shù)資料
| 型號(hào)： | IXF440 |
| 英文描述： | LAN HUB CONTROLLER |
| 中文描述： | 局域網(wǎng)集線器控制器 |
| 文件頁(yè)數(shù)： | 26/100頁(yè) |
| 文件大?。?/td> | 1354K |
| 代理商： | IXF440 |
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IXF440 Multiport 10/100 Mbps Ethernet Controller
26
Datasheet
3.2.2.4
Transmit Status Register
This register handles the causes for transmit stops. All bits, except PKC bits, are reset upon reading
this register. The bits in this register are set only if packet transmission is programmed to be
stopped following the corresponding error in the transmit error mode register (TX_ERR_MOD).
Bit Name
Bit Number
Bit Description
PKC
7:6
Packet count.
Indicates the number of packets currently stored in the transmit FIFO. The
packet count is incremented while loading the first byte of a packet and
decremented following transmission of a packet. The packet count can get a
maximum value of 2.
—
5:3
RESERVED
XCL
2
Excessive collision.
Indicates that a packet was sent 16 times unsuccessfully due to consecutive
collisions.
LCL
1
Late collision.
Indicates that a collision has occurred after transmission of 64 bytes.
UNF
0
FIFO underflow.
Indicates that data was not available in the transmit FIFO during packet
transmission, after transmission of 64 bytes.
Access Rules
Register access
R
Value after reset
00H
A5989-01
7
6
PKC
TXMT_STT
XCL
LCL
UNF
5
4
3
2
1
0
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