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參數(shù)資料
| 型號(hào)： | IXF440 |
| 英文描述： | LAN HUB CONTROLLER |
| 中文描述： | 局域網(wǎng)集線器控制器 |
| 文件頁(yè)數(shù)： | 28/100頁(yè) |
| 文件大小： | 1354K |
| 代理商： | IXF440 |
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IXF440 Multiport 10/100 Mbps Ethernet Controller
28
Datasheet
3.2.2.6
Port Control Register
The port control register handles all the control bits of the port.
Bit Name
Bit Number
Bit Description
—
7:6
RESERVED
TXSTT
5
Transmit restart.
When set, the chip restarts the transmission process after stopping due to a
transmit error. The TXSTT is a trigger bit (does not require reset before
setting).
TXEN
4
Transmit enable.
When this bit is set, the port enters the working mode. When reset, the port
completes transmission of the packet currently processed, and then stops.
Stop state is reported in the STOP bit located in the interrupt status register
(INT_STT).
RXEN
3
Receive enable.
When this bit is set, the port enters the working mode. When reset, the port
completes reception of the packet currently processed, and then stops. Stop
state is reported in the STOP bit located in the interrupt status register
(INT_STT).
PTRST
2
Port reset.
When set, this bit causes the transmit and receive logic to reset.
CTRST
1
Control reset.
When set, this bit resets all the registers, except PORT_CTR, to their default
values. Transmit and receive logic are also reset.
CNRST
0
Counter reset.
When set, this bit resets all the network statistic counters. The reset process
takes 100 cycles. During this time, the counters and PORT_CTR must not
be accessed. This bit must not be set together with the CTRST bit.
Access Rules
Register access
R/W
Value after reset
00H
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