
Datasheet
iii
IXF440 Multiport 10/100 Mbps Ethernet Controller
Contents
1.0
Introduction.........................................................................................................................9
1.1
General Description...............................................................................................9
1.2
IXF440 Block Diagram ..........................................................................................9
2.0
Pinout...............................................................................................................................11
2.1
Signal Descriptions..............................................................................................11
2.2
Pin Count.............................................................................................................16
2.3
Connection Rules................................................................................................16
2.4
Pin List.................................................................................................................17
3.0
Register Descriptions.......................................................................................................21
3.1
Register Conventions..........................................................................................21
3.1.1
Access Rules..........................................................................................21
3.2
CSR Register ......................................................................................................22
3.2.1
Register Mapping...................................................................................22
3.2.2
Base Registers.......................................................................................23
3.2.2.1 Chip Interrupt Summary Register..............................................23
3.2.2.2 Interrupt Status Register ...........................................................24
3.2.2.3 Interrupt Enable Register ..........................................................25
3.2.2.4 Transmit Status Register...........................................................26
3.2.2.5 Receive Status Register............................................................27
3.2.2.6 Port Control Register.................................................................28
3.2.2.7 Device ID Register ....................................................................29
3.2.2.8 Revision ID Register..................................................................29
3.2.2.9 Serial Command Register .........................................................30
3.2.3
Configuration Registers..........................................................................31
3.2.3.1 FIFO Threshold Register...........................................................31
3.2.3.2 IX Bus Mode Register ...............................................................32
3.2.3.3 Transmit Parameters Register ..................................................33
3.2.3.4 Transmit Error Mode Register...................................................34
3.2.3.5 Transmit Threshold and Backoff Register.................................35
3.2.3.6 Receive Parameters Register ...................................................36
3.2.3.7 Receive Filtering Mode Register ...............................................37
3.2.3.8 Transmit Pause Time Register..................................................38
3.2.3.9 Maximum Packet Size Register ................................................38
3.2.3.10InterPacket Gap Register..........................................................39
3.2.4
Serial Registers......................................................................................40
3.2.4.1 Serial Mode Register.................................................................40
3.2.4.2 Link Status Register ..................................................................41
3.2.4.3 Physical Address Register ........................................................41
3.3
Network Statistic Counter Mapping.....................................................................42
3.3.1
Register Mapping...................................................................................42
3.3.2
Network Statistic Counters Access Rules ..............................................44
3.4
Access Sequences..............................................................................................44
3.4.1
Initialization Sequence ...........................................................................44
3.4.2
Mode Change Sequence........................................................................44
3.4.3
Interrupt Handling Sequence..................................................................45