參數(shù)資料
型號(hào): IXF440
英文描述: LAN HUB CONTROLLER
中文描述: 局域網(wǎng)集線(xiàn)器控制器
文件頁(yè)數(shù): 44/100頁(yè)
文件大?。?/td> 1354K
代理商: IXF440
IXF440 Multiport 10/100 Mbps Ethernet Controller
44
Datasheet
3.3.2
Network Statistic Counters Access Rules
The network statistic counters access rules are as follows:
The counters can be accessed with a base address equal to 100H or 200H. Accessing the
counters with the 100H base address causes them to reset. Accessing them with the 200H will
not reset the counter.
Any of the counter bytes can be read without reading the other bytes. Only the accessed bytes
are reset (if accessed with the 100H base address).
The counters must be read from the lower to the upper bytes, in consecutive accesses.
The statistic counters are not writable.
Note:
Counter overflow causes it to remain fixed at the highest value it has reached.
Receive statistic counters are updated even upon receive FIFO overflow.
All the byte counters take CRC bytes into account, but exclude the framing bits in the packets.
3.4
Access Sequences
This section describes the initialization, mode change, and interrupt handling sequences for the
IXF440.
3.4.1
Initialization Sequence
Each IXF440 port must be initialized according to the following sequence:
1. Disable the port and reset it by writing:
06h to the port control register (PORT_CTR), and then
01h to the same register
2. Initialize the port by writing to the relevant configuration and serial registers.
3. Enable port operation by writing a value of 18h to the port control register (PORT_CTR).
3.4.2
Mode Change Sequence
In order to change the IXF440 working mode without impacting packet transfer, the following
sequence must be used:
1. Disable the port by writing a value of 00h to the port control register (PORT_CTR).
The number of correct received flow-control packets.
RX_PAUSE_CNT
C8H
CBH
The number of false carrier events detected.
RX_FALS_CRS_CNT
CCH
CFH
The number of received packets during which PHY symbol errors
were detected.
RX_SYM_ERR_CNT
D0H
D3H
Table 6. Network Statistic Register Mapping (Sheet 3 of 3)
Register Description
Mnemonic
I/O Address
Offset
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