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參數(shù)資料
| 型號： | IXF440 |
| 英文描述： | LAN HUB CONTROLLER |
| 中文描述： | 局域網(wǎng)集線器控制器 |
| 文件頁數(shù)： | 47/100頁 |
| 文件大?。?/td> | 1354K |
| 代理商： | IXF440 |
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IXF440 Multiport 10/100 Mbps Ethernet Controller
Datasheet
47
4.0
FIFO Interface Operation
This chapter describes the IXF440 FIFO interface operation, including the transmission and
reception flows.
4.1
FIFO Interface
The IXF440 uses a generic bus interface for data transfer to and from its FIFOs. The data bus is
64 bits wide but can be programmed to use only the lower 32-bits (FFO_BUS<BWID>). Big and
little endian byte ordering are both supported on 32-bit boundaries (FFO_BUS<BEND>). The
different FIFOs are accessed according to port selection signals (fps[2:0]) as well as transmit or
receive enabling signals (txsel_l, rxsel_l). Data transfer is synchronized to the main clock (clk), and
new data may be sent or received on each clock cycle. Each FIFO has a dedicated signal for each
direction (txrdy, rxrdy), reporting if it is ready for data transfer according to predetermined
thresholds (FFO_TSHD<TTH,RTH>). The burst size should be shorter than or equal to the
effective threshold. The amount of data transferred during a FIFO access may be dynamically
changed from one access to the other. On receive, if the FFO_BUS<HRYD> bit is reset, each first
burst of a packet should be shorter than or equal to the header size.
4.1.1
Byte Ordering on IX Bus
On the IX Bus, bytes are ordered according to the endian mode (FFO_BUS<BEND>) and the bus
width (FFO_BUS<BWID>).
Table 7
and
Table 8
show the different options for little endian mode.
Table 9
and
Table 10
show the different options for big endian mode.
Table 7. Little Endian, 64-Bit Bus (BEND=0, BWID=1)
63
32
31
0
8th byte
7th byte
6th byte
5th byte
4th byte
3rd byte
2nd byte
1st byte
Table 8. Little Endian, 32-Bit Bus (BEND=0, BWID=0)
31
0*
4th byte
3rd byte
2nd byte
1st byte
Table 9. Big Endian, 64-Bit Bus (BEND=1, BWID=1)
63
32
31
0
5th byte
6th byte
7th byte
8th byte
1st byte
2nd byte
3rd byte
4th byte
Table 10. Big Endian, 32-Bit Bus (BEND=1, BWID=0)
31
0*
1st byte
2nd byte
3rd byte
4th byte
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