參數(shù)資料
型號(hào)： IXF440
英文描述： LAN HUB CONTROLLER
中文描述： 局域網(wǎng)集線器控制器
文件頁(yè)數(shù)： 7/100頁(yè)
文件大?。?/td> 1354K
代理商： IXF440
Datasheet
vii
IXF440 Multiport 10/100 Mbps Ethernet Controller
Figures
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IXF440 Block Diagram ..........................................................................................9
Transmit Flow Diagram .......................................................................................51
Receive Flow Diagram ........................................................................................55
Transmit Start-of-Packet Timing..........................................................................71
Transmit End-of-Packet Timing...........................................................................72
Transmit FIFO Control Timing.............................................................................72
Transmit txrdy Timing..........................................................................................73
Receive Start-of-Packet Timing...........................................................................73
Receive End-of-Packet Timing............................................................................74
Fastest Receive Reaccess After EOP.................................................................74
Receive rxfail Timing...........................................................................................75
Receive rxabt Timing...........................................................................................75
Receive rxkep Timing..........................................................................................76
Receive Header Replay Timing...........................................................................76
Receive FIFO Control Timing..............................................................................76
Receive rxrdy Timing...........................................................................................77
Consecutive Transmit-Transmit Timing...............................................................77
Consecutive Transmit-Receive Timing................................................................78
Consecutive Receive-Transmit Timing................................................................78
Consecutive Receive-Receive Timing.................................................................78
Packet Transmission Timing...............................................................................79
Packet Reception Timing ....................................................................................79
Transmission with Collision Timing .....................................................................79
False Carrier Timing............................................................................................79
IX Bus Clock Timing Diagram .............................................................................83
IX Bus Signals Timing Diagram...........................................................................84
CPU Port Read Timing Diagram.........................................................................86
CPU Port Write Timing Diagram .........................................................................86
MII/SYM Clock Timing Diagram ..........................................................................88
MII/SYM Port Transmit Timing Diagram..............................................................88
MII/SYM Port Receive Timing Diagram...............................................................89
MII/SYM Port Carrier Sense and Collision Timing Diagram................................89
JTAG Port Timing Diagram .................................................................................90
Part Marking.......................................................................................................93
352-BGA Package - Bottom View.......................................................................93
Side View ............................................................................................................94
A
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A Section View................................................................................................94
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