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參數(shù)資料
| 型號： | IZ74LV174 |
| 廠商： | INTEGRAL JOINT STOCK COMPANY |
| 英文描述： | Hex D-type flip-flop with reset; positive edge-trigger |
| 中文描述： | 六角D型觸發(fā)器的復(fù)位觸發(fā)器，上升沿觸發(fā) |
| 文件頁數(shù)： | 4/6頁 |
| 文件大?。?/td> | 50K |
| 代理商： | IZ74LV174 |
IN74LV174
4
INTEGRAL
current per input
AC ELECTRICAL CHARACTERISTICS
(C
L
=50 pF, R
L
= 1 k
, t
r
=t
f
=2.5 ns)
Test
V
CC
Guaranteed Limit
85
°
C
max
min
Symbol
Parameter
conditions
V
-40
°
C to 25
°
C
125
°
C
min
Unit
min
max
max
t
PHL,
t
PLH
Propagation delay CP to
Qn
V
I
= 0 V or V
CC
Figure 1, 4
1.2
2.0
2.7
3.0
4.5
-
-
-
-
-
200
34
24
20
17
-
-
-
-
-
230
43
31
25
21
-
-
-
-
-
260
53
39
31
26
ns
t
PHL
Propagation delay MR to
Qn
V
I
= 0 V or V
CC
Figure 2, 4
1.2
2.0
2.7
3.0
4.5
-
-
-
-
-
160
34
24
20
17
-
-
-
-
-
190
43
31
25
21
-
-
-
-
-
220
53
39
31
26
ns
t
W
Clock pulse width HIGH or
LOW
V
I
= 0 V or V
CC
Figure 1, 4
1.2
2.0
2.7
3.0
4.5
100
28
21
17
14
-
-
-
-
-
140
34
25
20
17
-
-
-
-
-
180
41
30
24
20
-
-
-
-
-
ns
t
W
Master reset pulse width
LOW
V
I
= 0 V or V
CC
Figure 1, 4
1.2
2.0
2.7
3.0
4.5
100
28
21
17
14
-
-
-
-
-
140
34
25
20
17
-
-
-
-
-
180
41
30
24
20
-
-
-
-
-
ns
t
REM
Removal time MR to CP
V
I
= 0 V or V
CC
Figure 3, 4
1.2
2.0
2.7
3.0
4.5
40
19
13
11
9
-
-
-
-
-
60
22
16
13
11
-
-
-
-
-
80
26
19
15
13
-
-
-
-
-
ns
t
SU
Set-up time Dn to CP
V
I
= 0 or V
CC
Dèóí ê 3, 4
1.2
2.0
2.7
3.0
4.5
50
5
5
5
5
-
-
-
-
-
50
5
5
5
5
-
-
-
-
-
50
5
5
5
5
-
-
-
-
-
ns
t
h
Hold time Dn to CP
V
I
= 0 or V
CC
Dèóí ê 2, 4
1.2
2.0
2.7
3.0
4.5
50
5
5
5
5
-
-
-
-
-
50
5
5
5
5
-
-
-
-
-
50
5
5
5
5
-
-
-
-
-
ns
C
I
Input capacitance
ò
A
= 25
°
C
5.0
-
7.0
-
-
-
-
pF
C
PD
Power dissipation
capacitance (per flip-flop)
V
I
= 0 V or V
CC
T
A
= 25
°
C
5.5
-
34
-
-
-
-
pF
fmax
Maximum clock pulse
frequency
V
I
= 0 or V
CC
Dèóí ê 1
1.2
2.0
2.7
3.0
4.5
-
-
-
-
-
2.0
16
22
27
32
-
-
-
-
-
1.0
14
19
24
27
-
-
-
-
-
1.0
12
16
20
24
MHz
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