參數(shù)資料
型號: JS28F256P30B85
廠商: INTEL CORP
元件分類: DRAM
英文描述: Intel StrataFlash Embedded Memory
中文描述: 16M X 16 FLASH 1.8V PROM, 88 ns, PDSO56
封裝: 14 X 20 MM, LEAD FREE, TSOP-56
文件頁數(shù): 68/102頁
文件大?。?/td> 1609K
代理商: JS28F256P30B85
1-Gbit P30 Family
April 2005
68
Intel StrataFlash
Embedded Memory (P30)
Order Number: 306666, Revision: 001
Datasheet
To read data from the device (other than an erase-suspended block), the Read Array command must
be issued. During Erase Suspend, a Program command can be issued to any block other than the
erase-suspended block. Block erase cannot resume until program operations initiated during erase
suspend complete. Read Array, Read Status Register, Read Device Identifier, CFI Query, and Erase
Resume are valid commands during Erase Suspend. Additionally, Clear Status Register, Program,
Program Suspend, Block Lock, Block Unlock, and Block Lock-Down are valid commands during
Erase Suspend.
During an erase suspend, deasserting CE# places the device in standby, reducing active current.
V
PP
must remain at a valid level, and WP# must remain unchanged while in erase suspend. If
RST# is asserted, the device is reset.
12.3
Erase Resume
The Erase Resume command instructs the device to continue erasing, and automatically clears
status register bits SR[7,6]. This command can be written to any address. If status register error bits
are set, the Status Register should be cleared before issuing the next instruction. RST# must remain
deasserted (see
Figure 41, “Program Suspend/Resume Flowchart” on page 86
).
12.4
Erase Protection
When V
PP
= V
IL
, absolute hardware erase protection is provided for all device blocks. If V
PP
is
below V
PPLK
, erase operations halt and SR[3] is set indicating a V
PP
-level error.
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