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參數(shù)資料
| 型號： | JS28F256P30T85 |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | Intel StrataFlash Embedded Memory |
| 中文描述： | 16M X 16 FLASH 1.8V PROM, 88 ns, PDSO56 |
| 封裝： | 14 X 20 MM, LEAD FREE, TSOP-56 |
| 文件頁數(shù)： | 64/102頁 |
| 文件大?。?/td> | 1609K |
| 代理商： | JS28F256P30T85 |
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1-Gbit P30 Family
April 2005
64
Intel StrataFlash
Embedded Memory (P30)
Order Number: 306666, Revision: 001
Datasheet
11.3.1
BEFP Requirements and Considerations
BEFP requirements:
Case temperature: T
C
= 25
°C
± 5
°C
V
CC
within specified operating range
VPP driven to V
PPH
Target block unlocked before issuing the BEFP Setup and Confirm commands
The first-word address (WA0) for the block to be programmed must be held constant from the
setup phase through all data streaming into the target block, until transition to the exit phase is
desired
WA0 must align with the start of an array buffer boundary
1
BEFP considerations:
For optimum performance, cycling must be limited below 100 erase cycles per block
2
BEFP programs one block at a time; all buffer data must fall within a single block
3
BEFP cannot be suspended
Programming to the flash memory array can occur only when the buffer is full
4
NOTES:
1.
Word buffer boundaries in the array are determined by A[4:0] (0x00 through 0x1F). The alignment start
point is A[4:0] = 0x00.
2.
Some degradation in performance may occur if this limit is exceeded, but the internal algorithm
continues to work properly.
3.
If the internal address counter increments beyond the block's maximum address, addressing wraps
around to the beginning of the block.
4.
If the number of words is less than 32, remaining locations must be filled with 0xFFFF.
11.3.2
BEFP Setup Phase
After receiving the BEFP Setup and Confirm command sequence, Status Register bit SR[7]
(Ready) is cleared, indicating that the WSM is busy with BEFP algorithm startup. A delay before
checking SR[7] is required to allow the WSM enough time to perform all of its setups and checks
(Block-Lock status, V
PP
level, etc.). If an error is detected, SR[4] is set and BEFP operation
terminates. If the block was found to be locked, SR[1] is also set. SR[3] is set if the error occurred
due to an incorrect V
PP
level.
Note:
Reading from the device after the BEFP Setup and Confirm command sequence outputs Status
Register data. Do not issue the Read Status Register command; it will be interpreted as data to be
loaded into the buffer.
11.3.3
BEFP Program/Verify Phase
After the BEFP Setup Phase has completed, the host programming system must check SR[7,0] to
determine the availability of the write buffer for data streaming. SR[7] cleared indicates the device
is busy and the BEFP program/verify phase is activated. SR[0] indicates the write buffer is
available.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| JS28F256P30T95 | 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:Numonyx StrataFlash Embedded Memory |
| JS28F256P30T95A | 功能描述:IC FLASH 256MBIT 95NS 56TSOP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:StrataFlash™ 標(biāo)準(zhǔn)包裝:1 系列:- 格式 - 存儲器:RAM 存儲器類型:SDRAM 存儲容量:256M（8Mx32） 速度:143MHz 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:托盤 其它名稱:Q2841869 |
| JS28F256P30TF | 制造商:Intel 功能描述: 制造商:Intel 功能描述:16M X 16 FLASH 1.8V PROM, PDSO56 制造商:Numonyx BV 功能描述:16M X 16 FLASH 1.8V PROM, PDSO56 |
| JS28F256P30TFA | 功能描述:IC FLASH 256MBIT 110NS 56TSOP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:Axcell™ 產(chǎn)品變化通告:Product Discontinuation 26/Apr/2010 標(biāo)準(zhǔn)包裝:136 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步，DDR II 存儲容量:18M（1M x 18） 速度:200MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.9 V 工作溫度:0°C ~ 70°C 封裝/外殼:165-TBGA 供應(yīng)商設(shè)備封裝:165-CABGA（13x15） 包裝:托盤 其它名稱:71P71804S200BQ |
| JS28F256P30TFE | 功能描述:IC FLASH 256MBIT 56TSOP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:Axcell™ 標(biāo)準(zhǔn)包裝:2,000 系列:MoBL® 格式 - 存儲器:RAM 存儲器類型:SRAM - 異步 存儲容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并聯(lián) 電源電壓:2.2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFBGA 供應(yīng)商設(shè)備封裝:48-VFBGA（6x8） 包裝:帶卷 (TR) |
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