參數(shù)資料
型號(hào)： K3S7V2000M-TC12
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 64M-Bit (4Mx16 /2Mx32) Synchronous MASKROM
中文描述： 6400位（4Mx16 / 2Mx32）同步MASKROM
文件頁(yè)數(shù)： 10/27頁(yè)
文件大小： 1080K
代理商： K3S7V2000M-TC12
K3S7V2000M-TC
Synch. MROM
MODE REGISTER SET (MRS)
The mode register stores the data for controlling the various operating modes of SMROM. It programs the RAS latency, CAS latency,
burst length, burst type. On power-up, the mode register is set to the default value defined by the user requirement. When and if the
user wants to change its values, the user must exit from power down mode and start mode register set before entering normal oper-
ation mode. The mode register is reprogrammed by asserting low on CS, RAS, CAS and MR (The SMROM should be in active mode
with CKE already high prior to writing the mode register). The state of address pins A
0
~ A
7
in the same cycle as CS, RAS, CAS and
MR going low is the data written in the mode register. Three clock cycles are required to complete the program in the mode register,
therefore after mode register set command is completed, no new commands can be issued for 3 clock cycles and CS or MR must be
fixed to high within 3 clock cycles. The mode register is divided into various fields depending on functionality. The burst length field
uses A
0
~ A
1
, burst type uses A
2
, CAS latency (read latency from column address) uses A
3
~ A
5,
RAS latency uses
A
6
(RAS to CAS
delay). Refer to the table for specific codes for various burst length, burst type, CAS latencies and RAS latencies.
LATENCY
There are latencies between the issuance of a Row active command and when data is available on the I/O buffers. The RAS to CAS
delay is defined as the RAS latency. The CAS to data out delay is the CAS latency. The CAS and RAS latencies are programmable
through the mode register. RAS latencies of 1 and 2, and CAS latencies of 3 through 6 are supported. It is understood that some
RAS and CAS latency values are reserved for future use, and may not be available in the first generation for SMROM. The followings
are the supported minimum values in the first generation. RAS latency=2, and CAS latency=5 for 100MHz operation, and RAS
latency=2, and CAS latency=5 for 83MHz operation, and RAS latency=1, and CAS latency=4 for 66MHz operation, and RAS
latency=1, and CAS latenecy=4 for 50MHz operation, and RAS latency=1, and CAS latenecy=3 for 33MHz operation.
DQM OPERATION
The DQM is used to mask output operations when a complete burst read is not required. It works similar to OE during a read opera-
tion. The read latency is two cycles from DQM, which means DQM masking occurs two cycles later in the read cycle. DQM operation
is synchronous with the clock. The masking occurs for a complete cycle. (Also refer to the DQM timing diagram)
BURST READ
The burst read command is used to access a burst of data on consecutive clock cycles from an active row state. The burst read com-
mand is issued by asserting low CS and CAS with MR being high on the rising edge of the clock. The first output appears in CAS
latency number of clock cycles after the issuance of the burst read command. The burst length, burst sequence and latency from the
burst read command are determined by the mode register which is already programmed. Burst read can be initiated on any column
address of the active row. The output goes into high-impedance at the end of the burst, unless a new burst read is initiated to keep
the data output gapless. The burst read can be terminated by issuing another burst read.
DEVICE OPERATIONS
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