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參數(shù)資料
| 型號： | K4B1G0846C-CF8 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1Gb C-die DDR3 SDRAM Specification |
| 中文描述： | 1Gb的?芯片的DDR3 SDRAM規(guī)范 |
| 文件頁數(shù)： | 15/63頁 |
| 文件大?。?/td> | 1255K |
| 代理商： | K4B1G0846C-CF8 |
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Page 15 of 63
Rev. 1.0 June 2007
1Gb DDR3 SDRAM
K4B1G04(08/16)46C
[ Table 7 ] Single Ended AC and DC input levels
Note :
1. For DQ and DM, V
REF
= V
REFDQ
. For input only pins except RESET, or V
REF
= V
REFCA
2. See 9.6 "Overshoot and Undershoot specifications" on page 23.
3. The ac peak noise on V
REF
may not allow V
REF
to deviate from V
REF(DC)
by more than
±
1% VDD (for reference : approx.
±
15mV)
4. For reference : approx. VDD/2
±
15mV
Symbol
Parameter
DDR3-800/1066/1333
Unit
Notes
Min.
Max.
V
IH
(DC)
dc input logic high
VREF + 100
VDD
mV
1
V
IL
(DC)
dc input logic low
VSS
VREF - 100
mV
1
V
IH
(AC)
ac input logic high
VREF + 175
-
mV
1,2
V
IL
(AC)
ac input logic low
-
VREF - 175
mV
1,2
V
REF
DQ
(DC)
I/O Reference Voltage(DQ)
0.49*VDDQ
0.51*VDDQ
V
3,4
V
REF
CA
(DC)
I/O Reference Voltage(CMD/ADD)
0.49*VDDQ
0.51*VDDQ
V
3,4
8.0 AC & DC Input Measurement Levels
The dc-tolerance limits and ac-noise limits for the reference voltages V
REFCA
and V
REFDQ
are illustrate in Figure 1. It shows a valid reference voltage
VREF(t) as a function of time. (VREF stands for VREFCA and VREFDQ likewise).
VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requiremts in above
table. Furthermore VREF(t) may temporarily deviate from VREF(DC) by no more than
±
1% VDD.
voltage
VDD
VSS
V
Ref
ac-noise
V
Ref
(DC)
V
Ref
(DC)max
VDD/2
V
Ref
(DC)min
time
V
Ref
(DC)
8.1 AC and DC Logic input levels for single-ended signals
Figure 1. Illustration of VREF(DC) tolerance and VREF ac-noise limits
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VRef.
"VRef" shall be understood as VRef(DC), as defined in Figure 1.
This clarifies, that dc-variations of VRef affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to
which setup and hold is measured. System timing and voltage budgets need to account for VRef(DC) deviations from the optimum position within the
data-eye of the input signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VRef ac-noise. Timing
and voltage effects due to ac-noise on VRef up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings.
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