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參數(shù)資料
| 型號： | K4B1G0846C-CF8 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1Gb C-die DDR3 SDRAM Specification |
| 中文描述： | 1Gb的?芯片的DDR3 SDRAM規(guī)范 |
| 文件頁數(shù)： | 59/63頁 |
| 文件大?。?/td> | 1255K |
| 代理商： | K4B1G0846C-CF8 |
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Page 59 of 63
Rev. 1.0 June 2007
1Gb DDR3 SDRAM
K4B1G04(08/16)46C
Data Setup, Hold and Slew Rate Derating:
For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS(base) and tDH(base) value (see
Table 57) to the
tDS and
tDH (see Table 58) derating value respectively. Example: tDS (total setup time) = tDS(base) +
tDS.
Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of VIH(ac)min.
Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of VIL(ac)max
(see Figure 27). If the actual signal is always earlier than the nominal slew rate line between shaded ’VREF(dc) to ac region’, use nominal slew rate for
derating value. If the actual signal is later than the nominal slew rate line anywhere
between shaded ’VREF(dc) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value (see
Figure 29).
Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the first crossing of VREF(dc).
Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(dc)min and the first crossing of VREF(dc)
(see Figure 28). If the actual signal is always later than the nominal slew rate line between shaded ’dc level to VREF(dc) region’, use nominal slew rate for
derating value. If the actual signal is earlier than the nominal slew rate line anywhere between shaded ’dc to VREF(dc) region’, the slew rate of a tangent
line to the actual signal from the dc level to VREF(dc) level is used for derating value (see Figure 30).
For a valid transition the input signal has to remain above/below VIH/IL(ac) for some time tVAC (see Table 59).
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac) at the time of the rising clock
transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).
For slew rates in between the values listed in the tables the derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization
[ Table 57 ] Data Setup and Hold Base-Value
Note :
AC/DC referenced for 1V/ns DQ-slew rate and 2 V/ns DQS slew rate)
[ Table 58 ] Derating values DDR3-800/1066 tIS/tIH-ac/dc based
Note : a. Cell contents shaded in red are defined as ’not supported’.
[ Table 59 ] Required time t
VAC
above VIH(ac) {blow VIL(ac)} for valid transition
[ps]
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
reference
tDS(base)
75
25
-10
TBD
V
IH/L(ac)
V
IH/L(dc)
tDH(base)
150
100
65
TBD
tDS,
tDH Derating [ps] AC/DC based
a
DQS,DQS Differential Slew Rate
2.0 V/ns
1.8 V/ns
tDS
tDH
tDS
88
50
-
59
34
67
0
0
8
-2
-4
6
-6
-10
2
-
-
-3
-
-
-
-
-
-
-
-
-
4.0 V/ns
tDS
88
59
0
-
-
-
-
-
-
3.0 V/ns
tDS
88
59
0
-2
-
-
-
-
-
1.6 V/ns
tDS
-
-
16
14
10
5
-1
-
-
1.4V/ns
tDS
-
-
-
22
18
13
7
-11
-
1.2V/ns
tDS
-
-
-
-
26
21
15
-2
-30
1.0V/ns
tDS
-
-
-
-
-
29
23
6
-22
tDH
50
34
0
-
-
-
-
-
-
tDH
50
34
0
-4
-
-
-
-
-
tDH
-
45
8
4
-2
-8
-
-
-
tDH
-
-
16
12
6
0
-10
-
-
tDH
-
-
-
20
14
8
-2
-16
-
tDH
-
-
-
-
24
18
8
-6
-26
tDH
-
-
-
-
-
34
24
10
-10
DQ
Slew
rate
V/ns
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
Slew Rate[V/ns]
t
VAC
[ps]
min
max
>2.0
75
-
2.0
57
-
1.5
50
-
1.0
38
-
0.9
34
-
0.8
29
-
0.7
22
-
0.6
13
-
0.5
0
-
<0.5
0
-
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