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參數資料
| 型號： | K4B1G0846C-ZCF7 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1Gb C-die DDR3 SDRAM Specification |
| 中文描述： | 1Gb的?芯片的DDR3 SDRAM規(guī)范 |
| 文件頁數： | 17/63頁 |
| 文件大小： | 1255K |
| 代理商： | K4B1G0846C-ZCF7 |
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Page 17 of 63
Rev. 1.0 June 2007
1Gb DDR3 SDRAM
K4B1G04(08/16)46C
Figure 3: Single-ended requirement for differential signals.
Note that while ADD/CMD and DQ signal requirements are with respect to Vref, the single-ended components of differential signals have
a requirement with respect to VDD/2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to
measure setup time. For single-ended components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing
on timing, but adds a restriction on the common mode charateristics of these signals.
VDD or VDDQ
VSEH min
VDD/2 or VDDQ/2
VSEL max
VSEH
VSS or VSSQ
VSEL
CK or DQS
time
8.2.1 Single-ended requirements for differential signals
Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU) has also to comply with certain
requirements for single-ended signals.
CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels ( VIH(ac) / VIL(ac) ) for ADD/CMD
signals) in every half-cycle.
DQS, DQSL, DQSU, DQS, DQSL have to reach VSEHmin / VSELmax (approximately the ac-levels ( VIH(ac) / VIL(ac) ) for DQ signals)
in every half-cycle preceeding and following a valid transition.
Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g. if VIH150(ac)/VIL150(ac) is used for
ADD/CMD signals, then these ac-levels apply also for the single-ended signals CK and CK
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| K4B1G0846D-HCF8 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Gb D-die DDR3 SDRAM Specification |
| K4B1G0846D-HCH9 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Gb D-die DDR3 SDRAM Specification |
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