參數(shù)資料
型號(hào)： K4C560838C-TCD3
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 256Mb Network-DRAM
中文描述： 256Mb的網(wǎng)絡(luò)內(nèi)存
文件頁數(shù)： 11/42頁
文件大?。?/td> 880K
代理商： K4C560838C-TCD3
K4C5608/1638C 256Mb Network-DRAM
REV. 0.7 Aug. 2003
- 11 -
AC Characteristics and Operating Conditions
(Notes : 1, 2)
Symbol
Item
D4(400Mbps)
Min
DA(366Mbps)
Min
D3(333Mbps)
Min
Units Notes
Max
Max
Max
t
RC
Random Cycle Time
25
-
27.5
-
30
-
ns
3
t
CK
Clock Cycle Time
CL = 3
5.5
7.5
6
7.5
6.5
7.5
3
CL = 4
5
7.5
5.5
7.5
6
7.5
3
t
RAC
Random Access Time
-
22
-
24
-
26
3
t
CH
Clock High Time
0.45*t
CK
-
0.45*t
CK
-
0.45*t
CK
-
3
t
CL
Clock Low Time
0.45*t
CK
-
0.45*t
CK
-
0.45*t
CK
-
3
t
CKQS
DQS Access Time from CLK
-0.65
0.65
-0.75
0.75
-0.85
0.85
3, 8
t
QSQ
Data Output Skew from DQS
-
0.4
-
0.45
-
0.5
4
t
AC
Data Access Time from CLK
-0.65
0.65
-0.75
0.75
-0.85
0.85
3, 8
t
OH
Data Output Hold Time from CLK
-0.65
0.65
-0.75
0.75
-0.85
0.85
3, 8
t
QSPRE
DQS(Read) Preamble Pulse Width
0.9*t
CK
-0.2
1.1*t
CK
+0.2
0.9*t
CK
-0.2
1.1*t
CK
+0.2
0.9*t
CK
-0.2
1.1*t
CK
+0.2
3
t
HP
CLK half period ( minium of Actual t
CH
, t
CL
)
min(t
CH
, t
CL
)
-
min(t
CH
, t
CL
)
-
min(t
CH
, t
CL
)
-
t
QSP
DQS(Read) Pulse Width
t
HP
-0.55
-
t
HP
-0.6
-
t
HP
-0.65
-
4
t
QSQV
Data Output Valid Time from DQS
t
HP
-0.55
-
t
HP
-0.6
t
HP
-0.65
-
4
t
DQSS
DQS(Write) Low to High Setup Time
0.75*t
CK
1.25*t
CK
0.75*t
CK
1.25*t
CK
0.75*t
CK
1.25*t
CK
3
t
DSPRE
DQS(Write) Preamble Pulse Width
0.4*t
CK
-
0.4*t
CK
-
0.4*t
CK
-
4
t
DSPRES
DQS First Input Setup Time
0
-
0
-
0
-
3
t
DSPREH
DQS First Low Input Hold Time
0.25*t
CK
-
0.25*t
CK
-
0.25*t
CK
-
3
t
DSP
DQS High or Low Input Pulse Width
0.45*t
CK
0.55*t
CK
0.45*t
CK
0.55*t
CK
0.45*t
CK
0.55*t
CK
4
t
DSS
DQS Input Falling Edge to Clock Setup Time
CL = 3
1.3
-
1.4
-
1.5
-
3, 4
CL = 4
1.3
-
1.4
-
1.5
-
3, 4
t
DSPST
DQS(Write) Postamble Pulse Width
0.45*t
CK
-
0.45*t
CK
0.45*t
CK
-
4
t
DSPSTH
DQS(Write) Postamble Hold Time
CL = 3
1.3
-
1.4
-
1.5
-
3, 4
CL = 4
1.3
-
1.4
-
1.5
-
3, 4
t
DSSK
UDQS - LDQS Skew (x16)
-0.5*t
CK
0.5*t
CK
-0.5*t
CK
0.5*t
CK
-0.5*t
CK
0.5*t
CK
t
DS
Data Input Setup Time from DQS
0.5
-
0.5
-
0.6
-
4
t
DH
Data Input Hold Time from DQS
0.5
-
0.5
-
0.6
-
4
t
DIPW
Data Input pulse Width (for each device)
1.5
-
1.5
-
1.9
-
t
IS
Command / Address Input Setup Time
0.9
-
0.9
-
1
-
3
t
IH
Command / Address Input Hold Time
0.9
-
0.9
-
1
-
3
t
IPW
Command / Address Input Pulse Width (for each device)
2.0
-
2.0
-
2.2
-
t
LZ
Data-out Low Impedance Time from CLK
-0.65
-
-0.75
-
-0.85
-
3, 6, 8
t
HZ
Data-out High Impedance Time from CLK
-
0.65
-
0.75
-
0.85
3, 7, 8
t
QSLZ
DQS-out Low Impedance Time from CLK
-0.65
-
-0.75
-
-0.85
-
3, 6, 8
t
QSHZ
DQS-out High Impedance Time from CLK
-0.65
0.65
-0.75
0.75
-0.85
0.85
3, 7, 8
t
QPDH
Last Output to PD High Hold Time
0
-
0
-
0
-
t
PDEX
Power Down Exit Time
2
-
2
-
2
-
3
t
T
Input Transition Time
0.1
1
0.1
1
0.1
1
t
FPDL
PD Low Input Window for Self-Refresh Entry
-0.5*t
CK
5
-0.5*t
CK
5
-0.5*t
CK
5
3
相關(guān)PDF資料
PDF描述
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