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參數(shù)資料
| 型號： | K4C561638C-TCD4000 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Aluminum Electrolytic Radial Lead High Ripple, Long Life Capacitor; Capacitance: 47uF; Voltage: 200V; Case Size: 12.5x20 mm; Packaging: Bulk |
| 中文描述： | 256Mb的網(wǎng)絡內存 |
| 文件頁數(shù)： | 13/42頁 |
| 文件大小： | 880K |
| 代理商： | K4C561638C-TCD4000 |
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K4C5608/1638C 256Mb Network-DRAM
REV. 0.7 Aug. 2003
- 13 -
AC Test Conditions
Symbol
V
IH
(min)
V
IL
(max)
V
REF
V
TT
V
SWING
V
R
V
ID
(AC)
SLEW
V
OTR
Parameter
Value
Units
Notes
Input high voltage (minimum)
V
REF
+ 0.35
V
REF
- 0.35
V
Input low voltage (maximum)
V
Input reference voltage
VddQ/2
V
Termination voltage
V
REF
V
Input signal peak to peak swing
1.0
V
Differential clock input reference level
V
X(AC)
V
Input differential voltage
1.5
V
Input signal minimum slew rate
1.0
V/ns
Output timing measurement reference voltage
VddQ/2
V
V
IH
min
(AC)
V
REF
V
IL
max
(AC)
V
SWING
VddQ
Vss
Z=50
R
T
=50
V
TT
CL=30pF
V
REF
=0.5*VddQ
Measurement Point
Output
Output Load Circuit(SSTL_2)
Slew=(V
IH
min
(AC)
- V
IL
max
(AC)
)/
T
T
T
Notes :
1. Transition times are measured between V
IH
min
(DC)
and V
IL
max
(DC)
.
Transition (rise and fall) of input signals have a fixed slope.
2. If the result of nominal calculation with regard to t
CK
contains more than
one decimal place, the result is rounded up to the nearest decimal place.
(i.e., t
DQSS
= 0.75*t
CK
, t
CK
= 5ns, 0.75*5ns = 3.75ns is rounded up to 3.8ns.)
3. These parameters are measured from the differential clock (CK and CK) AC cross point.
4. These parameters are measured from signal transition point of DQS crossing V
REF
level.
5. The t
REFI
(MAX.) applies to equally distributed refresh method.
The t
REFI
(MIN.) applies to both burst refresh method and distributed refresh method.
In such case, the average interval of eight consecutive Auto-Refresh commands has to be more than 400ns always. In
other words, the number of Auto- Refresh cycles which can be performed within 3.2us (8X400ns) is to 8 times in the
maximum.
6. Low Impedance State is speified at VddQ/2± 0.2V from steady state.
7. High Impedance State is specified where output buffer is no longer driven.
8. These parameters depend on the clock jitter. These parameters are measured at stable clock.
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相關代理商/技術參數(shù) |
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