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參數(shù)資料
| 型號(hào)： | K4C561638C-TCDA |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256Mb Network-DRAM |
| 中文描述： | 256Mb的網(wǎng)絡(luò)內(nèi)存 |
| 文件頁(yè)數(shù)： | 41/42頁(yè) |
| 文件大小： | 880K |
| 代理商： | K4C561638C-TCDA |
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K4C5608/1638C 256Mb Network-DRAM
REV. 0.7 Aug. 2003
- 41 -
Functional Description (Continued)
Addressing sequence of Inteleave mode
A column access is started from the inputted lower address and is performed by interleaving the address bits in the
sequence shown as the following.
Addressing sequence for Interleave mode
(R-3) CAS Latency field (A6 to A4)
This field specifies the number of clock cycles from the assertion of the LAL command following the RDA command to
the first data read. The minimum values of CAS Latency depends on the frequency of CK. In a write mode, the place of
clock which should input write data is CAS Latency cycles - 1.
(R-4) Test Mode field (A7)
This bit is used to enter Test Mode for supplier only and must be set to "0" for normal operation.
(R-5) Reserved field in the Regular Mode Register
Reserved bits (A8 to A14)
These bits are reserved for future operations. They must be set to "0" for normal operation.
Data
Data 0
Data 1
Data 2
Data 3
Access Address
...A8 A7 A6 A5 A4 A3 A2 A1 A0
...A8 A7 A6 A5 A4 A3 A2 A1 A0
...A8 A7 A6 A5 A4 A3 A2 A1 A0
...A8 A7 A6 A5 A4 A3 A2 A1 A0
Burst Length
2 words
4 words
A6
0
0
0
0
1
1
1
1
A5
0
0
1
1
0
0
1
1
A4
0
1
0
1
0
1
0
1
CAS
Latency
Reserved
Reserved
Reserved
3
4
Reserved
Reserved
Reserved
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| K4C89083AF-ACF5 | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:288Mb x18 Network-DRAM2 Specification |
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