參數(shù)資料
型號(hào): K4C89323AF-GCF6
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 2,097,152-WORDS x 4 BANKS x 36-BITS DOUBLE DATA RATE Network-DRAM
中文描述: 2097152 - 4字×銀行× 36位的雙數(shù)據(jù)速率網(wǎng)絡(luò)內(nèi)存
文件頁數(shù): 7/58頁
文件大小: 1340K
代理商: K4C89323AF-GCF6
K4C89363AF
REV. 0.0 Nov. 2002
- 7 -
1. All voltages are referenced to Vss, VssQ.
2. V
REF
is expected to track variations in VddQ DC level of the transmitting device.
Peak to peak AC noise on V
REF
may not exceed ± 2% of V
REF
(DC).
3. Overshoot Iimit : V
IH
(max.) = VddQ + 0.7V with a pulse width <= 5ns
4. Undershoot Iimit : V
IL
(min.) = -0.7V with a pulse width <= 5ns
5. V
IH
(DC) and V
IL
(DC) are levels to maintain the current logic state.
6. V
IH
(AC) and V
IL
(AC) are levels to change to the new logic state.
7. V
ID
is magnitude of the difference between CLK input level and C L K input level.
8. The value of Vx(AC) is expected to equal VddQ/2 of the transmitting device.
9. V
ISO
means [V
I C K
(CLK) + V
I C K
(C L K )]/2
10. Refer to the figure below.
Notes
:
11. In the case of external termination, VTT(Termination Voltage) should be gone in the range of V
REF
( D C ) ±0 . 0 4 V .
Pin Capacitance
(V
DD
= 2.5V, V
D D Q
= 1.8V, f = 1 MHz, Ta = 25
o
C
)
Note :
These parameters are periodically sampled and not 100% tested.
S y m b o l
Parameter
Min
M a x
Delts
Units
C
IN
Input Pin Capacitance
1.5
2.5
0.25
pF
C
INC
Clock Pin (CLK, C L K ) Capacitance
1.5
2.5
0.25
pF
C
I/O
DQ, DS, QS Capacitance
2.5
3.5
0.5
pF
C
NC
NC Pin Capacitance
-
1.5
-
pF
CLK
CLK
V
SS
V
ID
( A C )
0 V Differential
V
ISO
V
SS
V
ICK
V
ISO
(min)
V
X
V
X
V
X
V
X
V
I C K
V
I C K
V
I C K
V
I S O
(max)
V
X
V
ID
(AC)
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