參數(shù)資料
型號(hào): K4C89323AF-TCF5
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 2,097,152-WORDS x 4 BANKS x 36-BITS DOUBLE DATA RATE Network-DRAM
中文描述: 2097152 - 4字×銀行× 36位的雙數(shù)據(jù)速率網(wǎng)絡(luò)內(nèi)存
文件頁(yè)數(shù): 11/58頁(yè)
文件大?。?/td> 1340K
代理商: K4C89323AF-TCF5
K4C89363AF
REV. 0.0 Nov. 2002
- 11 -
AC Test Conditions
S y m b o l
Parameter
V a l u e
Units
Notes
V
IH
(min)
Input high voltage (minimum)
V
REF
+ 0.2
V
V
IL
(max)
Input low voltage (maximum)
V
REF
- 0.2
V
V
REF
Input reference voltage
VddQ/2
V
V
TT
Termination voltage
V
REF
V
V
SWING
Input signal peak to peak swing
0.7
V
V
R
Differential clock input reference level
V
X(AC)
V
V
ID
( A C )
Input differential voltage
1.0
V
S L E W
Input signal minimum slew rate
2.5
V/ns
V
OTR
Output timing measurement reference voltage
VddQ/2
V
9
V
IH
min
(AC)
V
REF
V
IL
m a x
(AC)
V
SWING
V d d Q
Vss
Z = 5 0
V
TT
O u t p u t
Slew=
(V
IH
min
( A C )
- V
IL
m a x
(AC)
)/
T
T
T
Notes :
1. Transition times are measured between V
IH
min
(DC)
and V
IL
m a x
(DC)
.
Transition (rise and fall) of input signals have a fixed slope.
2. If the result of nominal calculation with regard to t
CK
contains more than
one decimal place, the result is rounded up to the nearest decimal place.
(i.e., t
DQSS
= 0.8*t
CK
, t
CK
= 3.3ns, 0.8*3.3 ns = 2.64 ns is rounded up to 2.7 ns.)
3. These parameters are measured from the differential clock (CLK and C LK ) AC cross point.
4. These parameters are measured from signal transition point of D S crossing V
REF
level.
5. The t
R E F I
(MAX.) applies to equally distributed refresh method.
The t
R E F I
(MIN.) applies to both burst refresh method and distributed refresh method.
In such case, the average interval of eight consecutive Auto-Refresh commands has to be more than 400ns always. In
other words, the number of Auto- Refresh cycles which can be performed within 3.2us (8X400ns) is to 8 times in the
m a x i m u m .
6. Low Impedance State is speified at VddQ/2± 0.2V from steady state.
7. High Impedance State is specified where output buffer is no longer driven.
8. These parameters depend on the clock jitter. These parameters are measured at stable clock.
9. Output timing is measured by using Normal driver strength.
Z = 5 0
AC Test Load
25
50
V
TT
50
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