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參數資料
| 型號： | K4C89363AF-TCFB |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 2,097,152-WORDS x 4 BANKS x 36-BITS DOUBLE DATA RATE Network-DRAM |
| 中文描述： | 2097152 - 4字×銀行× 36位的雙數據速率網絡內存 |
| 文件頁數： | 49/58頁 |
| 文件大?。?/td> | 1340K |
| 代理商： | K4C89363AF-TCFB |
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K4C89363AF
- 49 -
REV. 0.0 Sep. 2002
0
2
3
4
5
m-1
m
m+1
1
Self-Refresh Entry Timing
CLK
CLK
WRA
REF
DESL
Command
Q x
DQ
(output)
l
R E F C
Hi-Z
～
～
Unidirectional DS/Free Running QS mode
l
R C D
=1cycle
t
FPDL (min)
l
P D V
* 2
Auto Refresh
t
F P D L ( m a x )
Self Refresh Entry
l
C K D
t
Q P D H
Hi-Z
～
～
～
～
～
1. is don’ t care.
2. PD must be brought to "Low" within the timing between t
F P D L
(min) and t
F P D L
(max) to Self
Refresh mode. When PD is brought to "Low" after I
P D V ,
K4C89183AD perform Auto Refresh and enter
Power down mode.
3. It is desirable that clock input is continued at least I
C K D
from REF command even though PD is
brought to "Low" for Self-Refresh Entry.
Note :
Unidirectional DS/Free Running QS mode
REF
* 5
DESL
Command
(output)
DQ
(output)
l
R E F C
～
0
3
m-1
m
m+1
m+2
～
～
n-1
n
n+1
～
p-1
p
1
WRA
*5
DESL
RDA
* 7
LAL
* 7
l
R E F C
Command (1st)
*6
Command (2nd)
*6
l
P D A =
2cycles
* 4
l
R C D =
1cycle
l
R C D =
1cycle
t
P D E X
1. is don’ t care.
2. Clock should be stable prior to PD = "High" if clock input is suspended in Self-Refresh mode.
3. DESL command must be asserted during I
R E F C
after PD is brought to "High"
4. l
P D A
is defined from the first clock rising edge after PD is brought to "High"
5. It is desirable that one Auto-Refresh command is issued just after Self-Refresh Exit before any other
operation.
6. Any command (except Read command) can be issued after l
R E F C
.
7. Read command (RDA +LAL) can be issued after l
L O C K
.
8. QS output is invalid until DLL lock from Self-Refresh exit.
Note :
Self-Refresh Exit
Self-Refresh Exit Timing
～
～
～
～
～
～
～
～
～
～
～
～
～
LQS/UQS
LQS/UQS
(output)
～
～
l
L O C K
～
～
CLK
CLK
PD
PD
Hi-Z
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