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參數(shù)資料
| 型號(hào)： | K4D261638E |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 2M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM |
| 中文描述： | 200萬(wàn)× 16 × 4，銀行雙數(shù)據(jù)速率同步DRAM |
| 文件頁(yè)數(shù)： | 11/16頁(yè) |
| 文件大小： | 215K |
| 代理商： | K4D261638E |
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128M DDR SDRAM
K4D261638E
- 11 -
Rev. 1.2 (Jul. 2003)
DC CHARACTERISTICS
Note :
1. Measured with outputs open.
2. Refresh period is 32ms.
Parameter
Symbol
Test Condition
Version
Unit Note
-2A
-33
-36
-40
-50
Operating Current
(One Bank Active)
I
CC1
Burst Lenth=2
t
RC
≥
t
RC
(min)
I
OL
=0mA,
t
CC
=
t
CC
(min)
TBD
210
200
190
170
mA
1
Precharge Standby Current
in Power-down mode
I
CC2
P
CKE
≤
V
IL
(max),
t
CC
=
t
CC
(min)
TBD
70
mA
Precharge Standby Current
in Non Power-down mode
I
CC2
N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min),
t
CC
=
t
CC
(min)
TBD
100
90
80
70
mA
Active Standby Current
power-down mode
I
CC3
P
CKE
≤
V
IL
(max),
t
CC
=
t
CC
(min)
TBD
80
75
70
65
mA
Active Standby Current in
in Non Power-down mode
I
CC3
N
CKE
≥
VIH(min), CS
≥
VIH(min),
t
CC
=
t
CC
(min)
TBD
150
140
130
120
mA
Operating Current
( Burst Mode)
I
CC4
t
RC
≥
t
RFC
(min)
t
RC
≥
t
RFC
(min)
Page Burst, All Banks activated.
TBD
380
360
340
320
mA
Refresh Current
I
CC5
t
RC
≥
t
RFC
(min)
TBD
320
310
290
270
mA
2
Self Refresh Current
I
CC6
CKE
≤
0.2V
TBD
4
mA
Recommended operating conditions Unless Otherwise Noted, T
A
=0 to 65
°
C)
1. V
ID
is the magnitude of the difference between the input level on CK and the input level on CK
2. The value of V
IX
is expected to equal 0.5*V
DDQ
of the transmitting device and must track variations in the DC level of the same
3. For the K4D261638E-TC2A, VDD & VDDQ = 2.8V+0.1V.
Note :
AC INPUT OPERATING CONDITIONS
Recommended operating conditions(Voltage referenced to V
SS
=0V, V
DD
=2.5V+
5%, V
DDQ
=2.5V+
5%,T
A
=0 to 65
°
C)
Parameter
Symbol
Min
Typ
Max
Unit
Note
Input High (Logic 1) Voltage; DQ
V
IH
V
REF
+0.35
-
-
V
Input Low (Logic 0) Voltage; DQ
V
IL
-
-
V
REF
-0.35
V
Clock Input Differential Voltage; CK and CK
V
ID
0.7
-
V
DDQ
+0.6
V
1
Clock Input Crossing Point Voltage; CK and CK
V
IX
0.5*V
DDQ
-0.2
-
0.5*V
DDQ
+0.2
V
2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K4D261638E-TC2A | 2M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM |
| K4D261638E-TC33 | 2M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM |
| K4D261638E-TC36 | 2M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM |
| K4D261638E-TC40 | 2M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM |
| K4D261638E-TC50 | 2M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K4D261638E-TC2A | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:2M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM |
| K4D261638E-TC33 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:2M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM |
| K4D261638E-TC36 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:2M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM |
| K4D261638E-TC40 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:2M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM |
| K4D261638E-TC50 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:2M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM |
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