參數(shù)資料
型號: K4D553235F-GC33
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 256M GDDR SDRAM
中文描述: 256M GDDR SDRAM內(nèi)存
文件頁數(shù): 3/18頁
文件大?。?/td> 386K
代理商: K4D553235F-GC33
256M GDDR SDRAM
K4D553235F-GC
- 3 -
Rev 1.6 (May 2005)
The K4D553235F is 268,435,456 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 2,097,152 words by
32 bits, fabricated with SAMSUNG
s high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to 3.6GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety
of high performance memory system applications.
1.8V ± 0.1V power supply for device operation
1.8V ± 0.1V power supply for I/O interface
SSTL_18 compatible inputs/outputs
4 banks operation
MRS cycle with address key programs
-. Read latency 4, 5 and 6 (clock)
-. Burst length (2, 4 and 8)
-. Burst type (sequential & interleave)
All inputs except data & DM are sampled at the positive
going edge of the system clock
Differential clock input
GENERAL DESCRIPTION
FEATURES
No Wrtie-Interrupted by Read Function
4 DQS’s ( 1DQS / Byte )
Data I/O transactions on both edges of Data strobe
DLL aligns DQ and DQS transitions with Clock transition
Edge aligned data & data strobe output
Center aligned data & data strobe input
DM for write masking only
Auto & Self refresh
32ms refresh period (4K cycle)
144-Ball FBGA
Maximum clock frequency up to 450MHz
Maximum data rate up to 900Mbps/pin
FOR 2M x 32Bit x 4 Bank DDR SDRAM
2M x 32Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM
with Bi-directional Data Strobe and DLL
ORDERING INFORMATION
* K4D553235F-VC is the Lead Free package part number.
Part NO.
Max Freq.
Max Data Rate
Interface
Package
K4D553235F-GC25
400MHz
800Mbps/pin
SSTL_18
144-Ball FBGA
K4D553235F-GC2A
350MHz
700Mbps/pin
K4D553235F-GC33
300MHz
600Mbps/pin
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