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參數(shù)資料
| 型號： | K4D553238F-JC33 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256Mbit GDDR SDRAM |
| 中文描述： | 片256Mbit GDDR SDRAM內(nèi)存 |
| 文件頁數(shù)： | 7/17頁 |
| 文件大?。?/td> | 297K |
| 代理商： | K4D553238F-JC33 |
256M GDDR SDRAM
K4D553238F-JC
- 7 -
Rev 1.0 (Mar. 2004)
Power-Up Sequence
GDDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
1. Apply power and keep CKE at low state (All other inputs may be undefined)
- Apply VDD before VDDQ .
- Apply VDDQ before VREF & VTT
2. Start clock and maintain stable condition for minimum 200us.
3. The minimum of 200us after stable power and clock(CK,CK ), apply NOP and take CKE to be high .
4. Issue precharge command for all banks of the device.
5. Issue a EMRS command to enable DLL
*1
6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL.
*
1,2
7. Issue precharge command for all banks of the device.
8. Issue at least 2 or more auto-refresh commands.
9. Issue a mode register set command with A8 to low to initialize the mode register.
*1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL.
*2 Sequence of 6&7 is regardless of the order.
FUNCTIONAL DESCRIPTION
Power up & Initialization Sequence
Command
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
tRP
2 Clock min.
precharge
ALL Banks
2nd Auto
Refresh
Mode
Register Set
CoAny
t
RFC
~
1st Auto
Refresh
t
RFC
~
EMRS
MRS
2 Clock min.
DLL Reset
~
~
precharge
ALL Banks
t
RP
Inputs must be
stable for 200us
~
200 Clock min.
~
2 Clock min.
CK,CK
* When the operating frequency is changed, DLL reset should be required again.
After DLL reset again, the minimum 200 cycles of clock input is needed to lock the DLL.
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| K4D553238F-JC36 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mbit GDDR SDRAM |
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