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參數(shù)資料
| 型號(hào)： | K4M28163LF-R1L |
| 廠(chǎng)商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 2M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA |
| 中文描述： | 200萬(wàn)× 16 × 4銀行在54FBGA移動(dòng)SDRAM |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大小： | 115K |
| 代理商： | K4M28163LF-R1L |
K4M28163LF - R(B)E/N/S/C/L/R
February 2004
8
Mobile-SDRAM
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
NOTES :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Parameter
Symbol
-75
-1H
-1L
Unit
Note
Min
Max
Min
Max
Min
Max
CLK cycle time
CAS latency=3
t
CC
7.5
1000
9.5
1000
9.5
1000
ns
1
CLK cycle time
CAS latency=2
t
CC
9.5
9.5
12
CLK cycle time
CAS latency=1
t
CC
-
-
25
CLK to valid output delay
CAS latency=3
t
SAC
5.4
7
7
ns
1,2
CLK to valid output delay
CAS latency=2
t
SAC
7
7
8
CLK to valid output delay
CAS latency=1
t
SAC
-
-
20
Output data hold time
CAS latency=3
t
OH
2.5
2.5
2.5
ns
2
Output data hold time
CAS latency=2
t
OH
2.5
2.5
2.5
Output data hold time
CAS latency=1
t
OH
-
-
2.5
CLK high pulse width
t
CH
2.5
3.0
3.0
ns
3
CLK low pulse width
t
CL
2.5
3.0
3.0
ns
3
Input setup time
t
SS
2.0
2.5
2.5
ns
3
Input hold time
t
SH
1.0
1.5
1.5
ns
3
CLK to output in Low-Z
t
SLZ
1
1
1
ns
2
CLK to output in Hi-Z
CAS latency=3
t
SHZ
5.4
7
7
ns
CAS latency=2
7
7
8
CAS latency=1
-
-
20
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| K4M28163LF-R75 | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:2M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA |
| K4M28163LF-RE | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:2M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA |
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| K4M28163LF-S | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:2M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA |
| K4M28163LH | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:Mobile SDRAM |
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