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參數(shù)資料
| 型號： | K4N51163QC-ZC25 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | ; Filter Type:RFI; Current Rating:180A; Voltage Rating:480V; Series:FN258 RoHS Compliant: Yes |
| 中文描述： | 512MB的GDDR2 SDRAM的 |
| 文件頁數(shù)： | 3/64頁 |
| 文件大?。?/td> | 1420K |
| 代理商： | K4N51163QC-ZC25 |
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- 3 -
Rev 1.5 Oct. 2005
512M gDDR2 SDRAM
K4N51163QC-ZC
8M x 16Bit x 4 Banks graphic DDR2 Synchronous DRAM
with Differential Data Strobe
1.8V + 0.1V power supply for device operation
1.8V + 0.1V power supply for I/O interface
4 Banks operation
Posted CAS
Programmable CAS Letency : 3,4,5
Programmable Additive Latency : 0, 1, 2, 3 and 4
Write Latency (WL) = Read Latency (RL) -1
Burst Legth : 4 and 8 (Interleave/nibble sequential)
Programmable Sequential/ Interleave Burst Mode
Bi-directional Differential Data-Strobe
(Single-ended data-strobe is an optional feature)
Off-chip Driver (OCD) Impedance Adjustment
On Die Termination
Refresh and Self Refresh
Average Refesh Period 7.8us at lower then T
CASE
85×C,
3.9us at 85×C < T
CASE
< 95 ×C
Lead Free 84 ball FBGA(RoHS compliant)
* K4N51163QC-ZC2A/36 can fully cover previsous K4N51163QF-ZC30/37(667Mbps/533Mbps) product.
* K4N51163QC-GC is the Leaded package part number.
Part NO.
Max Freq.
Max Data Rate
Interface
Package
K4N51163QC-ZC
2
5
400MHz
800Mbps/pin
SSTL
84 Ball FBGA
K4N51163QC-ZC
2
A
350MHz
700Mbps/pin
K4N51163QC-ZC33
300MHz
600Mbps/pin
K4N51163QC-ZC36
275MHz
550Mbps/pin
The 512Mb gDDR2 SDRAM chip is organized as 8Mbit x 16 I/O x 4banks banks device. This synchronous device achieve high speed
graphic double-data-rate transfer rates of up to 800Mb/sec/pin for general applications. The chip is designed to comply with the follow-
ing key gDDR2 SDRAM features such as posted CAS with additive latency, write latency = read latency - 1, Off-Chip Driver(OCD)
impedance adjustment and On Die Termination. All of the control and address inputs are synchronized with a pair of externally supplied
differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a
pair of bidirectional strobes (DQS and DQS) in a source synchronous fashion. A thirteen bit address bus is used to convey row, column,
and bank address information in a RAS/CAS multiplexing style. For example, 512Mb(x16) device receive 13/10/2 addressing. The
512Mb gDDR2 devices operate with a single 1.8V ± 0.1V power supply and 1.8V ± 0.1V VDDQ. The 512Mb gDDR2 devices are avail-
able in 84ball FBGAs(x16).
Note : The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.
FOR 8M x 16Bit x 4 Bank gDDR2 SDRAM
1.0 FEATURES
2.0 ORDERING INFORMATION
3.0 GENERAL DESCRIPTION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K4N51163QC-ZC2A | 512Mbit gDDR2 SDRAM |
| K4N51163QC-ZC33 | 512Mbit gDDR2 SDRAM |
| K4N51163QC-ZC36 | 512Mbit gDDR2 SDRAM |
| K4R271669B-N(M)CG6 | 256K x 16/18 bit x 32s banks Direct RDRAMTM |
| K4R271669B-N(M)CK7 | 256K x 16/18 bit x 32s banks Direct RDRAMTM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K4N51163QC-ZC2A | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mbit gDDR2 SDRAM |
| K4N51163QC-ZC33 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mbit gDDR2 SDRAM |
| K4N51163QC-ZC36 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mbit gDDR2 SDRAM |
| K4N51163QG | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:Graphic Memory |
| K4N51163QZ | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:Graphic Memory |
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