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參數(shù)資料
| 型號(hào)： | K4N51163QC-ZC2A |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512Mbit gDDR2 SDRAM |
| 中文描述： | 512MB的GDDR2 SDRAM的 |
| 文件頁數(shù)： | 13/64頁 |
| 文件大?。?/td> | 1420K |
| 代理商： | K4N51163QC-ZC2A |
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- 13 -
Rev 1.5 Oct. 2005
512M gDDR2 SDRAM
K4N51163QC-ZC
2. gDDR2 SDRAM AC timing reference load
Following figure represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise
representation of the typical system environment or a depiction of the actual load presented by a production tester. System designers will use IBIS or
other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (gen-
erally a coaxial transmission line terminated at the tester electronics).
VDDQ
The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing reference voltage level for differential sig-
nals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS) signal.
3. gDDR2 SDRAM output slew rate test load
Output slew rate is characterized under the test conditions as shown in the following figure.
VDDQ
4. Differential data strobe
gDDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS “Enable DQS” mode
bit; timing advantages of differential mode are realized in system design. The method by which the gDDR2 SDRAM pin timings are measured is mode
dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode,
these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by
design and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally
to VSS through a 20 ohm
to 10 K ohm
resisor to insure proper operation.
DUT
DQ
DQS
DQS
Output
V
TT
= V
DDQ
/2
25
Timing
reference
point
<AC Timing Reference Load>
DUT
DQ
DQS, DQS
Output
V
TT
= V
DDQ
/2
25
Test point
<Slew Rate Test Load>
t
DS
t
DS
t
DH
t
WPRE
t
WPST
t
DQSH
t
DQSL
DQS
DQS
D
DMin
DQS/
DQS
DQ
DM
t
DH
<Data input (write) timing>
DMin
DMin
DMin
D
D
D
V
IL
(ac)
V
IH
(ac)
V
(ac)
V
IH
(ac)
V
IL
(dc)
V
IH
(dc)
V
IL
(dc)
V
IH
(dc)
t
CH
t
CL
CK
CK
CK/CK
DQS/DQS
DQ
DQS
DQS
t
RPST
Q
t
RPRE
t
DQSQmax
t
QH
t
QH
t
DQSQmax
<Data output (read) timing>
Q
Q
Q
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