參數(shù)資料
型號: K4N51163QC-ZC2A
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 512Mbit gDDR2 SDRAM
中文描述: 512MB的GDDR2 SDRAM的
文件頁數(shù): 40/64頁
文件大小: 1420K
代理商: K4N51163QC-ZC2A
- 40 -
Rev 1.5 Oct. 2005
512M gDDR2 SDRAM
K4N51163QC-ZC
Burst Write Operation: RL = 3, WL = 2, tWR = 2 (AL=0, CL=3), BL = 4
CMD
NOP
NOP
NOP
NOP
Precharge
NOP
DQs
NOP
CK/CK
T0
T2
T1
T3
T4
T5
T6
T7
Tn
WRITE A
CAS
WL = RL - 1 = 2
DQS
< = t
DQSS
> = WR
DIN A
0
DIN A
1
DIN A
2
DIN A
3
Bank A
Activate
Completion of
the Burst Write
> = tRP
Burst Write followed by Burst Read: RL = 5 (AL=2, CL=3), WL = 4, tWTR = 2, BL = 4
CMD
NOP
NOP
NOP
NOP
DQ
CK/CK
T0
T2
T1
T3
T4
T5
T6
T7
T8
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
NOP
DQS
WL = RL - 1 = 4
Post CAS
READ A
NOP
RL =5
AL = 2
CL = 3
NOP
NOP
Write to Read = CL - 1 + BL/2 + tWTR
> = tWTR
T9
The minimum number of clock from the burst write command to the burst read command is [CL - 1 + BL/2 + tWTR]. This tWTR is not a
write recovery time (tWR) but the time required to transfer the 4bit write data from the input buffer into sense amplifiers in the array.
tWTR is defined in AC spec table of this data sheet.
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