參數(shù)資料
型號(hào)： K4N51163QC-ZC33
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 512Mbit gDDR2 SDRAM
中文描述： 512MB的GDDR2 SDRAM的
文件頁(yè)數(shù)： 33/64頁(yè)
文件大?。?/td> 1420K
代理商： K4N51163QC-ZC33
- 33 -
Rev 1.5 Oct. 2005
512M gDDR2 SDRAM
K4N51163QC-ZC
ADDRESS
CK / CK
T0
T2
T1
T3
Tn
Tn+1
Tn+2
Tn+3
COMMAND
Bank A
Row Addr.
Bank A
Activate
Bank A
Col. Addr.
. . . . . . . . . .
. . . . . . . . . .
. . . . . . . . . .
Internal RAS-CAS delay (>= t
RCDmin
)
: “H” or “L”
RAS Cycle time (
>= t
RC
)
additive latency delay (
AL
)
Read A
Post CAS
Bank B
Row Addr.
Bank B
Activate
Bank B
Col. Addr.
Read B
Post CAS
Bank A
Addr.
Bank A
Precharge
Bank B
Addr.
Bank B
Precharge
Bank A
Row Addr.
Active
Bank A
RAS - RAS delay time (>= t
RRD
)
Read Begins
RCD =1
Bank Active (>= t
RAS
)
Bank Precharge time (
>= t
RP
)
CAS-CAS delay time (t
CCD
)
Bank Activate Command Cycle: tRCD = 3, AL = 2, tRP = 3, tRRD = 2, tCCD = 2
Posted CAS operation is supported to make command and data bus efficient for sustainable bandwidths in gDDR2 SDRAM. In this
operation, the gDDR2 SDRAM allows a CAS read or write command to be issued immediately after the RAS bank activate command (or
any time during the RAS-CAS-delay time, tRCD, period). The command is held for the time of the Additive Latency (AL) before it is
issued inside the device. The Read Latency (RL) is controlled by the sum of AL and the CAS latency (CL). Therefore if a user chooses
to issue a R/W command before the tRCDmin, then AL (greater than 0) must be written into the EMR(1). The Write Latency (WL) is
always defined as RL - 1 (read latency -1) where read latency is defined as the sum of additive latency plus CAS latency (RL=AL+CL).
Read or Write operations using AL allow seamless bursts (refer to seamless operation timing diagram examples in Read burst and
Write burst section)
Bank Activate Command
Read and Write Access Modes
After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS high, CS and CAS low at the clock’s rising
edge. WE must also be defined at this time to determine whether the access cycle is a read operation (WE high) or a write operation (WE low).
The DDR2 SDRAM provides a fast column access operation. A single Read or Write Command will initiate a serial read or write operation on successive
clock cycles. The boundary of the burst cycle is strictly restricted to specific segments of the page length. For example, the 32Mbit x 4 I/O x 4 Bank chip
has a page length of 2048 bits (defined by CA0-CA9, CA11). The page length of 2048 is divided into 512 or 256 uniquely addressable boundary segments
depending on burst length, 512 for 4 bit burst, 256 for 8 bit burst respectively. A 4-bit or 8 bit burst operation will occur entirely within one of the 512 or 256
groups beginning with the column address supplied to the device during the Read or Write Command (CA0-CA9, CA11). The second, third and fourth
access will also occur within this group segment, however, the burst order is a function of the starting address, and the burst sequence.
A new burst access must not interrupt the previous 4 bit burst operation in case of BL = 4 setting. However, in case of BL = 8 setting, two cases of interrupt
by a new burst access are allowed, one reads interrupted by a read, the other writes interrupted by a write with 4 bit burst boundry respectively. The min-
imum CAS to CAS delay is defined by tCCD, and is a minimum of 2 clocks for read or write cycles.
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