參數(shù)資料
型號: K4N51163QC-ZC33
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 512Mbit gDDR2 SDRAM
中文描述: 512MB的GDDR2 SDRAM的
文件頁數(shù): 34/64頁
文件大小: 1420K
代理商: K4N51163QC-ZC33
- 34 -
Rev 1.5 Oct. 2005
512M gDDR2 SDRAM
K4N51163QC-ZC
Examples of posted CAS operation
Example 1 Read followed by a write to the same bank
[AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL - 1) = 4]
0
1
2
3
4
5
6
7
8
9
10
11
12
Active
Read
A-Bank
Write
Dout0Dout1 Dout2Dout3
Din0Din1Din2Din3
CK/CK
CMD
DQS/DQS
DQ
AL = 2
-1
> = tRCD
CL = 3
> = tRAC
WL = RL -1 = 4
RL = AL + CL = 5
Example 2 Read followed by a write to the same bank
[AL = 0 and CL = 3, RL = (AL + CL) = 3, WL = (RL - 1) = 2]
Active
Read
Write
Dout0Dout1 Dout2Dout3
Din0Din1Din2Din3
AL = 0
> = tRCD
CL = 3
> = tRAC
WL = RL -1 = 2
RL = AL + CL = 3
0
1
2
3
4
5
6
7
8
9
10
11
12
-1
CK/CK
CMD
DQS/DQS
DQ
Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read
cycle). The parameters that define how the burst mode will operate are burst sequence and burst length. gDDR2 SDRAM supports 4 bit
burst and 8 bit burst modes only. For 8 bit burst mode, full interleave address ordering is supported, however, sequential address order-
ing is nibble based for ease of implementation. The burst type, either sequential or interleaved, is programmable and defined by the
address bit 3 (A3) of the MRS, which is similar to the DDR SDRAM operation. Seamless burst read or write operations are supported.
Unlike DDR devices, interruption of a burst read or write cycle during BL = 4 mode operation is prohibited. However in case of BL = 8
mode, interruption of a burst read or write operation is limited to two cases, reads interrupted by a read, or writes interrupted by a write.
Therefore the Burst Stop command is not supported on gDDR2 SDRAM devices.
Posted CAS
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