參數(shù)資料
型號(hào)： K4N51163QC-ZC33
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 512Mbit gDDR2 SDRAM
中文描述： 512MB的GDDR2 SDRAM的
文件頁(yè)數(shù)： 39/64頁(yè)
文件大?。?/td> 1420K
代理商： K4N51163QC-ZC33
- 39 -
Rev 1.5 Oct. 2005
512M gDDR2 SDRAM
K4N51163QC-ZC
t
DS
t
DS
t
DH
t
WPRE
t
WPST
t
DQSH
t
DQSL
DQS
DQS
D
DMin
DQS/
DQS
DQ
DM
t
DH
DMin
IL
(ac)
DMin
DMin
IL
D
D
D
V
IL
(ac)
V
IH
(ac)
(ac)
V
IL
(dc)
V
IH
(dc)
V
(dc)
Burst Write Operation: RL = 5, WL = 4, tWR = 3 (AL=2, CL=3), BL = 4
CMD
DQs
CK/CK
T0
T2
T1
T3
T4
T5
T6
T7
Tn
DQS
NOP
NOP
NOP
NOP
NOP
NOP
NOP
WRITE A
Posted CAS
WL = RL - 1 = 4
< = t
DQSS
> = WR
DIN A
0
DIN A
1
DIN A
2
DIN A
3
Precharge
Completion of
the Burst Write
Burst Write Operation
The Burst Write command is initiated by having CS, CAS and WE low while holding RAS high at the rising edge of the clock. The address inputs determine
the starting column address. Write latency (WL) is defined by a read latency (RL) minus one and is equal to (AL + CL -1);and is the number of clocks of
delay that are required from the time the write command is registered to the clock edge associated to the first DQS strobe. A data strobe signal (DQS)
should be driven low (preamble) one clock prior to the WL. The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the
DQS following the preamble. The tDQSS specification must be satisfied for each positive DQS transition to its associated clock edge during write cycles.
The subsequent burst bit data are issued on successive edges of the DQS until the burst length is completed, which is 4 or 8 bit burst. When t he burst
has finished, any additional data supplied to the DQ pins will be ignored. The DQ Signal is ignored after the burst write operation is complete. The time
from the completion of the burst write to bank precharge is the write recovery time (WR).
DDR2 SDRAM pin timings are specified for either single ended mode or differen-tial mode depending on the setting of the EMRS “Enable DQS” mode
bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode de-
pendent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at the specified AC/DC levels. In
differential mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods
is guaranteed by design and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must
be tied externally to VSS through a 20 ohm to 10K ohm resistor to insure proper operation.
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