參數(shù)資料
型號(hào)： K4N51163QC-ZC33
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 512Mbit gDDR2 SDRAM
中文描述： 512MB的GDDR2 SDRAM的
文件頁(yè)數(shù)： 51/64頁(yè)
文件大小： 1420K
代理商： K4N51163QC-ZC33
- 51 -
Rev 1.5 Oct. 2005
512M gDDR2 SDRAM
K4N51163QC-ZC
Note :
1. The value of tRTP is decided by the equation : max( RU<tRTP/tCK>, 2) where RU stands for round up. This is required to cover the max tCK case,
which is 8 ns.
2. For a given bank, the precharge period of tRP should be counted from the latest precharge command issued to that bank. Similarly, the precharge
period of tRPall should be counted from the latest precharge all command ossued to the DRAM.
From Command
To Command
Minimum Delay beween”From Com-
mand” to “To Command”
Unit
Note
Read w/AP
Precharge ( to same Bank as Read w/AP)
AL + BL/2 + tRTP - 2 * tCK
clks
1, 2
Precharge All
AL + BL/2 + tRTP - 2 * tCK
clks
1, 2
Write w/AP
Precharge ( to same Bank as Write w/AP)
WL + BL/2 + WR
clks
2
Precharge All
WL + BL/2 + WR
clks
2
Precharge
Precharge ( to same Bank as Precharge)
1 * tCK
clks
2
Precharge All
1 * tCK
clks
2
Precharge All
Precharge
1 * tCK
clks
2
Precharge All
1 * tCK
clks
2
Refresh Command
When CS, RAS and CAS are held low and WE high at the rising edge of the clock, the chip enters the Refresh mode (REF). All banks
of the gDDR2 SDRAM must be precharged and idle for a minimum of the Precharge time (tRP) before the Refresh command (REF) can
be applied. An address counter, internal to the device, supplies the bank address during the refresh cycle. No control of the external
address bus is required once this cycle has started.
When the refresh cycle has completed, all banks of the gDDR2 SDRAM will be in the precharged (idle) state. A delay between the
Refresh command (REF) and the next Activate command or subsequent Refresh command must be greater than or equal to the
Refresh cycle time (tRFC).
To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided.
A maximum of eight Refresh commands can be posted to any given gDDR2 SDRAM, meaning that the maximum absolute interval
between any Refresh command and the next Refresh command is 9 * tREFI.
CMD
CK/CK
T0
T2
T1
T3
Tm
Tn
Tn + 1
CKE
> = t
RP
> = t
RFC
> = t
RFC
High
NOP
REF
REF
NOP
ANY
Precharge
NOP
Precharge & Auto Precharge Clarification
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