參數(shù)資料
型號： K4N51163QC-ZC36
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 512Mbit gDDR2 SDRAM
中文描述： 512MB的GDDR2 SDRAM的
文件頁數(shù)： 12/64頁
文件大?。?/td> 1420K
代理商： K4N51163QC-ZC36
- 12 -
Rev 1.5 Oct. 2005
512M gDDR2 SDRAM
K4N51163QC-ZC
Note : General notes, which may apply for all AC parameters
1. Slew Rate Measurement Levels
a. Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single ended signals. For differential signals
(e.g. DQS - DQS) output slew rate is measured between DQS - DQS = -500 mV and DQS - DQS = +500mV. Output slew rate is guaranteed by
design, but is not necessarily tested on each device.
b. Input slew rate for single ended signals is measured from dc-level to ac-level: from VREF - 125 mV to VREF + 250 mV for rising edges and from
VREF + 125 mV and VREF - 250 mV for falling edges. For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK =
-250 mV to CK - CK = +500 mV (250mV to -500 mV for falling egdes).
c. VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or between DQS and DQS for differential
strobe.
Parameter
Symbol
- 25
- 2A
-33
- 36
Units Notes
min
max
min
max
min
max
min
max
CAS to CAS command delay
tCCD
2
2
2
2
tCK
Write recovery time
tWR
6
x
5
x
5
x
4
x
tCK
Auto precharge write recovery + pre-
charge time
tDAL
WR+tRP
x
tWR
+tRP
x
tWR
+tRP
x
tWR
+tRP
x
tCK
23
Internal write to read command delay
tWTR
3
3
x
3
x
2
x
tCK
Internal read to precharge command
delay
tRTP
3
3
3
2
tCK
11
Exit self refresh to a non-read com-
mand
tXSNR
tRFC +
10
tRFC +
10
tRFC +
10
tRFC +
10
ns
Exit self refresh to a read command
tXSRD
200
200
200
200
tCK
Exit precharge power down to any
non-read command
tXP
2
x
2
x
2
x
2
x
tCK
Exit active power down to read com-
mand
tXARD
2
x
2
x
2
x
2
x
tCK
9
Exit active power down to read com-
mand
(Slow exit, Lower power)
tXARDS 8 - AL
6 - AL
6 - AL
6 - AL
tCK
9, 10
CKE minimum pulse width
(high and low pulse width)
tCKE
3
3
3
3
tCK
ODT turn-on delay
tAOND
2
2
2
2
2
2
2
2
tCK
ODT turn-on
tAON tAC(min)t)+0.7
tAC
(min)
tAC
(max)+0
.7
tAC
(min)
tAC
(max)+0
.7
tAC
(min)
tAC
(max)+1
ns
13, 25
ODT turn-on(Power-Down mode)
tAONPDtA+2
2tCK+tA
C(max)+
1
tAC
(min)+2
2tCK+
tAC(max
)+1
tAC
(min)+2
2tCK+
tAC(max
)+1
tAC
(min)+2
2tCK+tA
C(max)+
1
ns
ODT turn-off delay
tAOFD
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
tCK
ODT turn-off
tAOF tAC(min)t)+ 0.6
tAC
(min)
tAC
(max)+
0.6
tAC
(min)
tAC
(max)+
0.6
tAC
(min)
tAC
(max)+
0.6
ns
26
ODT turn-off (Power-Down mode)
tAOFPDtA+2
2.5tCK+
tAC(max
)+1
tAC(min)
+2
2.5tCK+t
AC(max)
+1
tAC(min)
+2
2.5tCK+t
AC(max)
+1
tAC(min)
+2
2.5tCK+
tAC(max
)+1
ns
ODT to power down entry latency
tANPD
3
3
3
3
tCK
ODT power down exit latency
tAXPD
8
8
8
8
tCK
OCD drive mode output delay
tOIT
0
12
0
12
0
12
0
12
ns
Minimum time clocks remains ON after
CKE asynchronously drops LOW
tDelay
tIS+tCK
+tIH
tIS+tCK
+tIH
tIS+tCK
+tIH
tIS+tCK
+tIH
ns
24
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