參數(shù)資料
型號： K4N51163QC-ZC
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 512Mbit gDDR2 SDRAM
中文描述： 512MB的GDDR2 SDRAM的
文件頁數(shù)： 17/64頁
文件大?。?/td> 1420K
代理商： K4N51163QC-ZC
- 17 -
Rev 1.5 Oct. 2005
512M gDDR2 SDRAM
K4N51163QC-ZC
29. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the V
IH(ac)
level to the differ-
ential data strobe crosspoint for a rising signal, and from the input signal crossing at the V
IL(ac)
level to the differential data strobe crosspoint for a
falling signal applied to the device under test.
30. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the V
IH(dc)
level to the differ-
ential data strobe crosspoint for a rising signal and V
IL(dc)
to the differential data strobe crosspoint for a falling signal applied to the device under
test.
Differential Input waveform timing
tDS
V
DDQ
V
IH
(AC) min
V
IH
(DC) min
V
REF
V
IL
(DC) max
V
IL
(AC) max
V
SS
DQS
DQS
tDH
tDS
tDH
<Data setup/hold timing>
3
3. tWTR is at lease two clocks (2 * tCK) independent of operation frequency.
34. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the VIH(ac) level to the sin-
gle-ended data strobe crossing VIH/L(dc) at the start of its transition for a rising signal, and from the input signal crossing at the VIL(ac) level to the
single-ended data strobe crossing VIH/L(dc) at the start of its transition for a falling signal applied to the device under test. The DQS signal must be
monotonic between Vil(dc)max and Vih(dc)min.
35. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the VIH(dc) level to the sin-
gle-ended data strobe crossing VIH/L(ac) at the end of its transition for a rising signal, and from the input signal crossing at the VIL(dc) level to the sin-
gle-ended data strobe crossing VIH/L(ac) at the end of its transition for a falling signal applied to the device under test. The DQS signal must be
monotonic between Vil(dc)max and Vih(dc)min.
36. tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire
time it takes to achieve the 3 clocks of registeration. Thus, after any cKE transition, CKE may not transitioin from its valid level during the time period
of tIS + 2*tCK + tIH.
31. Input waveform timing is referenced from the input signal crossing at the VIH(ac) level for a rising signal and VIL(ac) for a falling signal applied to the
device under test.
32. Input waveform timing is referenced from the input signal crossing at the VIL(dc) level for a rising signal and VIH(dc) for a falling signal applied to the
device under test.
tIS
V
DDQ
V
IH
(AC) min
V
IH
(DC) min
V
REF
V
IL
(DC) max
V
IL
(AC) max
V
SS
CK
CK
tIH
tIS
tIH
<Input setup/hold timing>
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