參數(shù)資料
型號(hào)： K4R271669B-N(M)CG6
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 256K x 16/18 bit x 32s banks Direct RDRAMTM
中文描述： 256 × 16/18位× 32秒銀行直接RDRAMTM
文件頁(yè)數(shù)： 5/20頁(yè)
文件大?。?/td> 306K
代理商： K4R271669B-N(M)CG6
Direct RDRAM
Page 3
K4R271669B/K4R441869B
Version 1.11 Oct. 2000
Table 2: Pin Description
Signal
I/O
Type
# of
Pins
Description
SIO1,SIO0
I/O
CMOS
a
2
Serial input/output. Pins for reading from and writing to the control regis-
ters using a serial access protocol. Also used for power management.
CMD
I
CMOS
a
1
Command input. Pins used in conjunction with SIO0 and SIO1 for reading
from and writing to the control registers. Also used for power manage-
ment.
SCK
I
CMOS
a
1
Serial clock input. Clock source used for reading from and writing to the
control registers
V
DD
10
Supply voltage for the RDRAM core and interface logic.
V
DDa
1
Supply voltage for the RDRAM analog circuitry.
V
CMOS
2
Supply voltage for CMOS input/output pins.
GND
13
Ground reference for RDRAM core and interface.
GNDa
1
Ground reference for RDRAM analog circuitry.
DQA8..DQA0
I/O
RSL
b
9
Data byte A. Nine pins which carry a byte of read or write data between
the Channel and the RDRAM. DQA8 is not used (no connection) by
RDRAMs with a x16 organization.
CFM
I
RSL
b
1
Clock from master. Interface clock used for receiving RSL signals from
the Channel. Positive polarity.
CFMN
I
RSL
b
1
Clock from master. Interface clock used for receiving RSL signals from
the Channel. Negative polarity
V
REF
1
Logic threshold reference voltage for RSL signals
CTMN
I
RSL
b
1
Clock to master. Interface clock used for transmitting RSL signals to the
Channel. Negative polarity.
CTM
I
RSL
b
1
Clock to master. Interface clock used for transmitting RSL signals to the
Channel. Positive polarity.
RQ7..RQ5 or
ROW2..ROW0
I
RSL
b
3
Row access control. Three pins containing control and address informa-
tion for row accesses.
RQ4..RQ0 or
COL4..COL0
I
RSL
b
5
Column access control. Five pins containing control and address informa-
tion for column accesses.
DQB8..
DQB0
I/O
RSL
b
9
Data byte B. Nine pins which carry a byte of read or write data between
the Channel and the RDRAM. DQB8 is not used (no connection) by
RDRAMs with a x16 organization.
Total pin count per package
62
a. All CMOS signals are high-true; a high voltage is a logic one and a low voltage is logic zero.
b. All RSL signals are low-true; a low voltage is a logic one and a high voltage is logic zero.
相關(guān)PDF資料
PDF描述
K4R271669B-N(M)CK7 256K x 16/18 bit x 32s banks Direct RDRAMTM
K4R271669B-Nb(M)CcK8 256K x 16/18 bit x 32s banks Direct RDRAMTM
K4R271669B 256K x 16/18 bit x 32s banks Direct RDRAMTM
K4R441869B 256K x 16/18 bit x 32s banks Direct RDRAMTM
K4R441869B-N(M)CG6 256K x 16/18 bit x 32s banks Direct RDRAMTM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
K4R271669D 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mbit RDRAM(D-die)
K4R271669D-T 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mbit RDRAM(D-die)
K4R271669D-TCS8 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mbit RDRAM(D-die)
K4R271669E 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mbit RDRAM(E-die)
K4R271669F 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mbit RDRAM(F-die)
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