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參數(shù)資料
| 型號： | K4R271669B-N(M)CK7 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256K x 16/18 bit x 32s banks Direct RDRAMTM |
| 中文描述： | 256 × 16/18位× 32秒銀行直接RDRAMTM |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 306K |
| 代理商： | K4R271669B-N(M)CK7 |
Direct RDRAM
Page 12
K4R271669B/K4R441869B
Version 1.11 Oct. 2000
Timing Conditions
Table 11: Timing Conditions
Symbol
Parameter
Min
Max
Unit
Figure(s)
t
CYCLE
CTM and CFM cycle times (-800)
2.50
3.83
ns
Figure 55
CTM and CFM cycle times (-711)
2.80
3.83
CTM and CFM cycle times (-600)
3.33
3.83
t
CR
, t
CF
CTM and CFM input rise and fall times. Use the minimum value
of these parameters during testing.
0.2
0.5
ns
Figure 55
t
CH
, t
CL
CTM and CFM high and low times
40%
60%
t
CYCLE
Figure 55
t
TR
CTM-CFM differential (MSE/MS=0/0)
CTM-CFM differential (MSE/MS=1/1)
0.0
0.9
1.0
1.0
t
CYCLE
Figure 43
Figure 55
t
DCW
Domain crossing window
-0.1
0.1
t
CYCLE
Figure 61
t
DR
, t
DQA/DQB/ROW/COL input rise/fall times (20% to 80%). Use
the minimum value of these parameters during testing.
0.2
0.65
ns
Figure 56
t
S
, t
H
DQA/DQB/ROW/COL-to-CFM set/hold @ t
CYCLE
=2.50ns
DQA/DQB/ROW/COL-to-CFM set/hold @ t
CYCLE
=2.81ns
DQA/DQB/ROW/COL-to-CFM set/hold @ t
CYCLE
=3.33ns
0.200
b
0.240
c,d
0.275
b,d
-
-
-
ns
Figure 56
t
DR1,
t
DF1
SIO0, SIO1 input rise and fall times
-
5.0
ns
Figure 58
t
DR2,
t
DF2
CMD, SCK input rise and fall times
-
2.0
ns
Figure 58
t
CYCLE1
SCK cycle time - Serial control register transactions
1000
-
ns
Figure 58
SCK cycle time - Power transitions
10
-
ns
Figure 58
t
CH1
, t
CL1
SCK high and low times
4.25
-
ns
Figure 58
t
S1
CMD setup time to SCK rising or falling edge
e
1.25
-
ns
Figure 58
t
H1
CMD hold time to SCK rising or falling edge
e
1
-
ns
Figure 58
t
S2
SIO0 setup time to SCK falling edge
40
-
ns
Figure 58
t
H2
SIO0 hold time to SCK falling edge
40
-
ns
Figure 58
t
S3
PDEV setup time on DQA5..0 to SCK rising edge.
0
-
ns
Figure 49
t
H3
PDEV hold time on DQA5..0 to SCK rising edge.
5.5
-
ns
Figure 59
t
S4
ROW2..0, COL4..0 setup time for quiet window
-1
-
t
CYCLE
Figure 49
t
H4
ROW2..0, COL4..0 hold time for quiet window
f
5
-
t
CYCLE
Figure 49
t
NPQ
Quiet on ROW/COL bits during NAP/PDN entry
4
-
t
CYCLE
Figure 48
t
READTOCC
Offset between read data and CC packets (same device)
12
-
t
CYCLE
Figure 53
t
CCSAMTOREAD
Offset between CC packet and read data (same device)
8
-
t
CYCLE
Figure 53
t
CE
CTM/CFM stable before NAP/PDN exit
2
-
t
CYCLE
Figure 49
t
CD
CTM/CFM stable after NAP/PDN entry
100
-
t
CYCLE
Figure 48
t
FRM
ROW packet to COL packet ATTN framing delay
7
-
t
CYCLE
Figure 47
t
NLIMIT
Maximum time in NAP mode
10.0
μ
s
Figure 46
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