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參數(shù)資料
| 型號： | K4R441869B-N(M)CG6 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256K x 16/18 bit x 32s banks Direct RDRAMTM |
| 中文描述： | 256 × 16/18位× 32秒銀行直接RDRAMTM |
| 文件頁數(shù)： | 18/20頁 |
| 文件大?。?/td> | 306K |
| 代理商： | K4R441869B-N(M)CG6 |
Direct RDRAM
Page 16
K4R271669B/K4R441869B
Version 1.11 Oct. 2000
Absolute Maximum Ratings
I
DD
- Supply Current Profile
Table 14: Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
V
I,ABS
Voltage applied to any RSL or CMOS pin with respect to Gnd
- 0.3
V
DD
+0.3
V
V
DD,ABS
, V
DDA,ABS
Voltage on VDD and VDDA with respect to Gnd
- 0.5
V
DD
+1.0
V
T
STORE
Storage temperature
- 50
100
°
C
Table 15: Supply Current Profile
I
DD
value
RDRAM Power State and Steady-State Transaction Rates
a
Min
Max
-45
-800
Max
-45
-711
Max
-53.3
-600
Unit
I
DD,PDN
Device in PDN, self-refresh enabled and INIT.LSR=0.
-
5000
5000
5000
μ
A
I
DD,NAP
Device in NAP.
-
4
4
4
mA
I
DD,STBY
Device in STBY. This is the average for a device in STBY with (1) no
packets on the Channel, and (2) with packets sent to other devices.
-
105
100
90
mA
I
DD,REFRESH
Device in STBY and refreshing rows at the t
REF,MAX
period.
-
105
100
90
mA
I
DD,ATTN
Device in ATTN. This is the average for a device in ATTN with (1) no
packets on the Channel, and (2) with packets sent to other devices.
-
165
155
140
mA
I
DD,ATTN-W
Device in ATTN. ACT command every 8t
CYCLE
, PRE command
every 8t
CYCLE
, WR command every 4
t
CYCLE
, and data is 1100..1100
-
575/
625
b
525/
580
455/
500
mA
I
DD,ATTN-R
Device in ATTN. ACT command every 8t
CYCLE
, PRE command
every 8
t
CYCLE
, RD command every 4
t
CYCLE
, and data is 1111..1111
c
-
490/
520
450/
480
400/
420
mA
a. CMOS interface consumes power in all power states.
b. x16/x18 RDRAM data width.
c. This does not include the I
OL
sink current. The RDRAM dissipates I
OL
V
OL
in each output driver when a logic one is driven.
Table 16: Supply Current at Initialization
Symbol
Parameter
Allowed Range of t
CYCLE
V
DD
Min
Max
Unit
I
DD,PWRUP,D
I
DD
from power -on to SETR
3.33ns to 3.83ns
2.50ns to 3.32ns
V
DD,MIN
-
150
a
200
b
mA
I
DD,SETR,D
I
DD
from SETR to CLRR
3.33ns to 3.83ns
2.50ns to 3.32ns
V
DD,MIN
-
250
b
332
b
mA
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