參數(shù)資料
型號: K4R441869B
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 256K x 16/18 bit x 32s banks Direct RDRAMTM
中文描述: 256 × 16/18位× 32秒銀行直接RDRAMTM
文件頁數(shù): 15/20頁
文件大?。?/td> 306K
代理商: K4R441869B
Direct RDRAM
Page 13
K4R271669B/K4R441869B
Version 1.11 Oct. 2000
a. MSE/MS are fields of the SKIP register. For this combination (skip override) the tDCW parameter range is effectively 0.0 to 0.0.
b. This parameter also applies to a -800 or -711 part when operated with t
CYCLE
=3.33ns.
c.
t
S,MIN
and t
H,MIN
for other t
CYCLE
values can be interpolated between or extrapolated from the timings at the 3 specified t
CYCLE
values.
d.
This parameter also applies to a -800 part when operated with t
CYCLE
=2.81ns.
e.
With V
IL,CMOS
=0.5V
CMOS
-0.4V and V
IH,CMOS
=0.5V
CMOS
+0.4V
f. Effective hold becomes t
H4
’=t
H4
+[PDNXA
64
t
SCYCLE
+t
PDNXB,MAX
]-[PDNX
256t
SCYCLE
]
if [PDNX
256
t
SCYCLE
] < [PDNXA
64
t
SCYCLE
+t
PDNXB,MAX
]. See Figure 49.
t
REF
Refresh interval
32
ms
Figure 51
t
BURST
Interval after PDN or NAP (with self-refresh) exit in which all
banks of the RDRAM must be refreshed at least once.
200
μ
s
Figure 52
t
CCTRL
Current control interval
34 t
CYCLE
100ms
ms/t
CYCLE
Figure 53
t
TEMP
Temperature control interval
100
ms
Figure 54
t
TCEN
TCE command to TCAL command
150
-
t
CYCLE
Figure 54
t
TCAL
TCAL command to quiet window
2
2
t
CYCLE
Figure 54
t
TCQUIET
Quiet window (no read data)
140
-
t
CYCLE
Figure 54
t
PAUSE
RDRAM delay (no RSL operations allowed)
200.0
μ
s
page 38
Table 11: Timing Conditions
Symbol
Parameter
Min
Max
Unit
Figure(s)
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