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參數資料
| 型號： | K4R761869A-FCM8 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 576Mbit RDRAM (A-die) 1M x 18bit x 32s banks Direct RDRAMTM |
| 中文描述： | 576Mbit的RDRAM（一模）100萬x 18位x 32秒銀行直接RDRAMTM |
| 文件頁數： | 15/20頁 |
| 文件大?。?/td> | 313K |
| 代理商： | K4R761869A-FCM8 |
Direct RDRAM
Page 13
K4R761869A
Version 1.41 Jan. 2004
t
S2
SIO0 setup time to SCK falling edge
40
-
ns
Figure 59
t
H2
SIO0 hold time to SCK falling edge
40
-
ns
Figure 59
t
S3
PDEV setup time on DQA5..0 to SCK rising edge.
0
-
ns
Figure 50
t
H3
PDEV hold time on DQA5..0 to SCK rising edge.
5.5
-
ns
Figure 60
t
S4
ROW2..0, COL4..0 setup time for quiet window
-1
-
t
CYCLE
Figure 50
t
H4
ROW2..0, COL4..0 hold time for quiet window
f
5
-
t
CYCLE
Figure 50
t
NPQ
Quiet on ROW/COL bits during NAP/PDN entry
4
-
t
CYCLE
Figure 49
t
READTOCC
Offset between read data and CC packets (same device)
12
-
t
CYCLE
Figure 54
t
CCSAMTOREAD
Offset between CC packet and read data (same device)
8
-
t
CYCLE
Figure 54
t
CE
CTM/CFM stable before NAP/PDN exit
2
-
t
CYCLE
Figure 50
t
CD
CTM/CFM stable after NAP/PDN entry
100
-
t
CYCLE
Figure 49
t
FRM
ROW packet to COL packet ATTN framing delay
7
-
t
CYCLE
Figure 48
t
NLIMIT
Maximum time in NAP mode
10.0
ms
Figure 47
t
REF
Refresh interval
32
ms
Figure 52
t
BURST
Interval after PDN or NAP (with self-refresh) exit in which all banks
of the RDRAM device must be refreshed at least once.
200
ms
Figure 53
t
CCTRL
Current control interval
34 t
CYCLE
100ms
ms/t
CYCLE
Figure 54
t
TEMP
Temperature control interval
100
ms
Figure 55
t
TCEN
TCE command to TCAL command
150
-
t
CYCLE
Figure 55
t
TCAL
TCAL command to quiet window
2
2
t
CYCLE
Figure 55
t
TCQUIET
Quiet window (no read data)
140
-
t
CYCLE
Figure 55
t
PAUSE
RDRAM device delay (no RSL operations allowed)
200.0
ms
page 38
a. MSE/MS are fields of the SKIP register. For this combination (skip override) the tDCW parameter range is effectively 0.0 to 0.0.
b.
t
S,MIN
and t
H,MIN
for other t
CYCLE
values can be interpolated between or extrapolated from the timings at the 2 specified t
CYCLE
values.
c. This parameter also applies to a-1200 part when operated with t
CYCLE
= 1.875ns
d. This parameter also applies to a-1200 or -1066 part when operated with t
CYCLE
= 2.50ns
e. With V
IL,CMOS
=0.5V
CMOS
-0.4V and V
IH,CMOS
=0.5V
CMOS
+0.4V
f. Effective hold becomes t
H4
’=t
H4
+[PDNXA64t
SCYCLE
+t
PDNXB,MAX
]-[PDNX256t
SCYCLE
] if [PDNX256t
SCYCLE
] < [PDNXA64t
SCYCLE
+t
PD-
NXB,MAX
]. See Figure 50
Table 11: Timing Conditions
Symbol
Parameter
Min
Max
Unit
Figure(s)
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相關代理商/技術參數 |
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| K4R761869A-FCT9 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:576Mbit RDRAM (A-die) 1M x 18bit x 32s banks Direct RDRAMTM |
| K4R761869A-GCM8 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:576Mbit RDRAM (A-die) 1M x 18bit x 32s banks Direct RDRAMTM |
| K4R761869A-GCN1 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:576Mbit RDRAM (A-die) 1M x 18bit x 32s banks Direct RDRAMTM |
| K4R761869A-GCT9 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:576Mbit RDRAM (A-die) 1M x 18bit x 32s banks Direct RDRAMTM |
| K4R761869A-GCT9000 | 制造商:Samsung Semiconductor 功能描述:512 DIRECT RDRAM X18 WBGA - Trays |
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