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參數(shù)資料
| 型號： | K4R761869A-FCT9 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 576Mbit RDRAM (A-die) 1M x 18bit x 32s banks Direct RDRAMTM |
| 中文描述： | 576Mbit的RDRAM（一模）100萬x 18位x 32秒銀行直接RDRAMTM |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 313K |
| 代理商： | K4R761869A-FCT9 |
Direct RDRAM
Page 10
Version 1.41 Jan. 2004
K4R761869A
Electrical Conditions
Table 9: Electrical Conditions
Symbol
Parameter and Conditions
Min
Max
Unit
T
J
Junction temperature under bias
-
100
°
C
V
DD,
V
DDA
Supply voltage
2.50 - 0.13
2.50 + 0.13
V
V
DD,N,
V
DDA,N
Supply voltage droop (DC) during NAP interval (t
NLIMIT
)
-
2.0
%
v
DD,N,
v
DDA,N
Supply voltage ripple (AC) during NAP interval (t
NLIMIT
)
-2.0
2.0
%
V
CMOSa
Supply voltage for CMOS pins (2.5V controllers)
Supply voltage for CMOS pins (1.8V controllers)
V
DD
1.80 - 0.1
V
DD
1.80 + 0.2
V
V
V
REF
Reference voltage
1.40 - 0.2
1.40 + 0.2
V
V
DIL
RSL data input - low voltage @ t
CYCLE
=1.667ns
V
REF
- 0.5
V
REF
- 0.15
V
RSL data input - low voltage @ t
CYCLE
=1.875ns
V
REF
- 0.5
V
REF
- 0.15
RSL data input - low voltage @ t
CYCLE
=2.50ns
V
REF
- 0.5
V
REF
- 0.2
V
DIH
RSL data input - high voltage
b
@ t
CYCLE
=1.667ns
V
REF
+ 0.15
V
REF
+ 0.5
RSL data input - high voltage
b
@ t
CYCLE
=1.875ns
V
REF
+ 0.15
V
REF
+ 0.5
V
RSL data input - high voltage
b
@ t
CYCLE
=2.50ns
V
REF
+ 0.2
V
REF
+ 0.5
R
DA
RSL data asymmetry : R
DA
= (V
DIH
- V
REF
) / (V
REF
- V
DIL
)
0.67
1.00
-
V
CM
RSL clock input - common mode V
CM
= (V
CIH
+V
CIL)
/2
1.3
1.8
V
V
CIS,CTM
RSL clock input swing: V
CIS
= V
CIH
- V
CIL
(CTM,CTMN pins).
0.35
1.00
V
V
CIS,CFM
RSL clock input swing: V
CIS
= V
CIH
- V
CIL
(CFM,CFMN pins).
0.225
1.00
V
V
IL,CMOS
CMOS input low voltage
- 0.3
c
V
CMOS
/2 - 0.25
V
V
IH,CMOS
CMOS input high voltage
V
CMOS
/2 + 0.25
V
CMOS
+0.3
d
V
a. V
CMOS
must remain on as long as V
DD
is applied and cannot be turned off.
b. V
DIH
is typically equal to V
TERM
(1.8V
±
0.1V) under DC conditions in a system.
c. Voltage undershoot is limited to -0.7V for a duration of less than 5ns.
d. Voltage overshoot is limited toV
CMOS
+0.7V for a duration of less than 5ns
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