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參數(shù)資料
| 型號： | K4R761869A-FCT9 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 576Mbit RDRAM (A-die) 1M x 18bit x 32s banks Direct RDRAMTM |
| 中文描述： | 576Mbit的RDRAM（一模）100萬x 18位x 32秒銀行直接RDRAMTM |
| 文件頁數(shù)： | 16/20頁 |
| 文件大小： | 313K |
| 代理商： | K4R761869A-FCT9 |
Direct RDRAM
Page 14
K4R761869A
Version 1.41 Jan. 2004
Timing Characteristics
Table 12: Timing Characteristics
Symbol
Parameter
Min
Max
Unit
Figure(s)
t
Q
CTM-to-DQA/DQB output time @ t
CYCLE
=1.667ns
-0.170
a
a. t
Q,MIN
and t
Q,MAX
for other t
CYCLE
values can be interpolated between or extrapolated from the timings at the 3 specified t
CYCLE
values.
b. This parameter also applies to a-1200 part when operated with t
CYCLE
= 1.875ns
c. This parameter also applies to a-1200 or -1066 part when operated with t
CYCLE
= 2.50ns
+0.170
a
ns
Figure 58
CTM-to-DQA/DQB output time @ t
CYCLE
=1.875ns
-0.195
a,b
+0.195
a,b
CTM-to-DQA/DQB output time @ t
CYCLE
=2.5ns
-0.260
a,c
+0.260
a,c
t
QR
, t
QF
DQA/DQB output rise and fall times @ t
CYCLE
=1.667ns
0.2
0.32
ns
Figure 58
DQA/DQB output rise and fall times @ t
CYCLE
=1.875ns
0.2
0.32
DQA/DQB output rise and fall times @ t
CYCLE
=2.5ns
0.2
0.45
t
Q1
SCK(neg)-to-SIO0 delay @ C
LOAD,MAX
= 20pF (SD read data valid).
-
10
ns
Figure 61
t
HR
SCK(pos)-to-SIO0 delay @ C
LOAD,MAX
= 20pF (SD read data hold).
2
-
ns
Figure 61
t
QR1
, t
QF1
SIO
OUT
rise/fall @ C
LOAD,MAX
= 20pF
-
12
ns
Figure 61
t
PROP1
SIO0-to-SIO1 or SIO1-to-SIO0 delay @ C
LOAD,MAX
= 20pF
-
20
ns
Figure 61
t
NAPXA
NAP exit delay - phase A
-
50
ns
Figure 50
t
NAPXB
NAP exit delay - phase B
-
40
ns
Figure 50
t
PDNXA
PDN exit delay - phase A
-
4
μ
s
Figure 50
t
PDNXB
PDN exit delay - phase B
-
9000
t
CYCLE
Figure 50
t
AS
ATTN-to-STBY power state delay
-
1
t
CYCLE
Figure 48
t
SA
STBY-to-ATTN power state delay
-
0
t
CYCLE
Figure 48
t
ASN
ATTN/STBY-to-NAP power state delay
-
8
t
CYCLE
Figure 49
t
ASP
ATTN/STBY-to-PDN power state delay
-
8
t
CYCLE
Figure 49
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