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參數資料
| 型號： | K4R881869 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| 中文描述： | 288Mbit RDRAM的為512k × 18位× 2 * 16屬銀行直接RDRAMTM |
| 文件頁數： | 30/64頁 |
| 文件大小： | 4084K |
| 代理商： | K4R881869 |
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Page 28
Direct RDRAM
K4R881869M
Rev. 0.9 Jan. 2000
Preliminary
Initialization
Initialization refers to the process that a controller must go
through after power is applied to the system or the system is
reset. The controller prepares the RDRAM sub-system for
normal Channel operation by (primarily) using a sequence of
control register transactions on the serial CMOS pins. The
following steps outline the sequence seen by the various
memory subsystem components (including the RDRAM
components) during initialization. This sequence is available
in the form of reference code.
1.0 Start Clocks
- This step calculates the proper clock
frequencies for PClk (controller logic), SynClk (RAC
block), RefClk (DRCG component), CTM (RDRAM
component), and SCK (SIO block).
2.0 RAC Initialization
- This step causes the INIT block to
generate a sequence of pulses which resets the RAC,
performs RAC maintainance operations, and measures
timing intervals in order to ensure clock stability.
3.0 RDRAM Initialization
- This stage performs most of
the steps needed to initialize the RDRAMs. The rest are
performed in stages 5.0, 6.0, and 7.0. All of the steps in 3.0
are carried out through the SIO block interface.
o
3.1/3.2 SIO Reset
- After a delay of t
PAUSE
from step
1.0, this reset operation is performed berore any SIO
control register read or write transactions. It clears six
registers (TEST34, CCA, CCB, SKIP, TEST78, and
TEST79) and places the INIT register into a special
state (all bits cleared except SKP and SDEVID fields
are set to ones).
o
3.3 Write TEST77 Register
- The TEST77 register
must be explicitly written with zeros before any other
registers are read or written.
o
3.4 Write TCYCLE Register
- The TCYCLE register
is written with the cycle time tCYCLE of the CTM
clock (for Channel and RDRAMs) in units of 64ps. The
tCYCLE value is determined in stage 1.0.
o
3.5 Write SDEVID Register
- The SDEVID (serial
device identification) register of each RDRAM is
written with a unique address value so that directed SIO
read and write transactions can be performed. This
address value increases from 0 to 31 according to the
distance an RDRAM is from the ASIC component on
the SIO bus (the closest RDRAM is address 0).
o
3.6 Write DEVID Register
- The DEVID (device iden-
tification) register of each RDRAM is written with a
unique address value so that directed memory read and
write transactions can be performed. This address value
increases from 0 to 31. The DEVID value is not neces-
sarily the same as the SDEVID value. RDRAMs are
sorted into regions of the same core configuration
(number of bank, row, and column address bits and core
type).
o
3.7 Write PDNX,PDNXA Registers
- The PDNX and
PDNXA registers are written with values that are used
to measure the timing intervals connected with an exit
from the PDN (powerdown) power state.
o
3.8 Write NAPX Register
- The NAPX register is
written with values that are used to measure the timing
intervals connected with an exit from the NAP power
state.
o
3.9 Write TPARM Register
- The TPARM register is
written with values which determine the time interval
between a COL packet with a memory read command
and the Q packet with the read data on the Channel. The
values written set each RDRAM to the minimum value
permitted for the system. This will be adjusted later in
stage 6.0.
o
3.10 Write TCDLY1 Register
- The TCDLY1 register
is written with values which determine the time interval
between a COL packet with a memory read command
and the Q packet with the read data on the Channel. The
values written set each RDRAM to the minimum value
permitted for the system. This will be adjusted later in
stage 6.0.
o
3.11 Write TFRM Register
- The TFRM register is
written with a value that is related to the t
RCD
parameter
for the system. The t
RCD
parameter is the time interval
Figure 26: SIO Reset Sequence
SCK
CMD
SIO0
T
16
0000000000000000
0000000000000000
00001100
SIO1
T
0
The packet is repeated
from SIO0 to SIO1
1
1
1
1
0
0
0
0
00000000...00000000
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