參數(shù)資料
型號(hào)： K4R881869
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM
中文描述： 288Mbit RDRAM的為512k × 18位× 2 * 16屬銀行直接RDRAMTM
文件頁(yè)數(shù)： 5/64頁(yè)
文件大?。?/td> 4084K
代理商： K4R881869
Page 3
Direct RDRAM
K4R881869M
Rev. 0.9 Jan. 2000
Preliminary
Table 2: Pin Description
Signal
I/O
Type
# Pins
Description
SIO1,SIO0
I/O
CMOS
a
2
Serial input/output. Pins for reading from and writing to the control
registers using a serial access protocol. Also used for power man-
agement.
CMD
I
CMOS
a
1
Command input. Pins used in conjunction with SIO0 and SIO1 for
reading from and writing to the control registers. Also used for
power management.
SCK
I
CMOS
a
1
Serial clock input. Clock source used for reading from and writing to
the control registers
V
DD
24
Supply voltage for the RDRAM core and interface logic.
V
DDa
1
Supply voltage for the RDRAM analog circuitry.
V
CMOS
2
Supply voltage for CMOS input/output pins.
GND
28
Ground reference for RDRAM core and interface.
GNDa
2
Ground reference for RDRAM analog circuitry.
DQA8..DQA0
I/O
RSL
b
9
Data byte A. Nine pins which carry a byte of read or write data
between the Channel and the RDRAM.
CFM
I
RSL
b
1
Clock from master. Interface clock used for receiving RSL signals
from the Channel. Positive polarity.
CFMN
I
RSL
b
1
Clock from master. Interface clock used for receiving RSL signals
from the Channel. Negative polarity
V
REF
1
Logic threshold reference voltage for RSL signals
CTMN
I
RSL
b
1
Clock to master. Interface clock used for transmitting RSL signals
to the Channel. Negative polarity.
CTM
I
RSL
b
1
Clock to master. Interface clock used for transmitting RSL signals
to the Channel. Positive polarity.
RQ7..RQ5 or
ROW2..ROW0
I
RSL
b
3
Row access control. Three pins containing control and address
information for row accesses.
RQ4..RQ0 or
COL4..COL0
I
RSL
b
5
Column access control. Five pins containing control and address
information for column accesses.
DQB8..
DQB0
I/O
RSL
b
9
Data byte B. Nine pins which carry a byte of read or write data
between the Channel and the RDRAM.
Total pin count per package
92
a. All CMOS signals are high-true; a high voltage is a logic one and a low voltage is logic zero.
b. All RSL signals are low-true; a low voltage is a logic one and a high voltage is logic zero.
相關(guān)PDF資料
PDF描述
K4R881869M 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM
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K4R881869M-NCK7 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
K4R881869D 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256/288Mbit RDRAM(D-die)
K4R881869D-FCM8 制造商:Samsung Electro-Mechanics 功能描述:16M X 18 DIRECT RAMBUS DRAM, PBGA92
K4R881869EFCT9 制造商:Samsung Semiconductor 功能描述:
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