參數(shù)資料
型號(hào)： K4R881869
廠(chǎng)商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM
中文描述： 288Mbit RDRAM的為512k × 18位× 2 * 16屬銀行直接RDRAMTM
文件頁(yè)數(shù)： 55/64頁(yè)
文件大?。?/td> 4084K
代理商： K4R881869
Page 53
Direct RDRAM
K4R881869M
Rev. 0.9 Jan. 2000
Preliminary
Figure 58 also shows the combinational path connecting
SIO0 to SIO1 and the path connecting SIO1 to SIO0 (read
data only). The t
PROP1
parameter specified this propagation
delay. The rise and fall times of SIO0 and SIO1 inputs must
be t
DR1
and t
DF1
, measured at the 20% and 80% levels. The
rise and fall times of SIO0 and SIO1 outputs are t
QR1
and
t
QF1
, measured at the 20% and 80% levels.
RSL - Domain Crossing Window
When read data is returned by the RDRAM, imformation
must cross from the receive clock domain (CFM) to the
transmit clock domain (CTM). The t
TR
parameter permits
the CFM to CTM phase to vary through an entire cycle; i.e.
there is no restriction on the alignment of these two clocks.
A second parameter t
DCW
is needed in order to describe how
the delay between a RD command packet and read data
packet varies as a function of the t
TR
value.
Figure 59 shows this timing for five distinct values of t
TR
.
Case A (t
TR
=0) is what has been used throughout this docu-
ment. The delay between the RD command and read data is
t
CAC
. As t
TR
varies from zero to t
CYCLE
(cases A through
E), the command to data delay is (t
CAC
-t
TR
). When the t
TR
value is in the range 0 to t
DCW,MAX
, the command to data
delay can also be (t
CAC
-t
TR
-t
CYCLE
). This is shown as cases
A’ and B’ (the gray packets). Similarly, when the t
TR
value
is in the range (t
CYCLE
+t
DCW,MIN
) to t
CYCLE
, the command
to data delay can also be (t
CAC
-t
TR
+t
CYCLE
). This is shown
as cases D’ and E’(the gray packets). The RDRAM will
work reliably with either the white or gray packet timing.
The delay value is selected at initialization, and remains
fixed thereafter.
Figure 59: RSL Transmit - Crossing Read Domains
CFM
COL
t
TR
CTM
DQA/B
DQA/B
t
TR
=0
t
CYCLE
Case A
t
TR
=0
Case A’
t
TR
CTM
DQA/B
DQA/B
t
TR
=t
DCW,MAX
Case B
t
TR
=t
DCW,MAX
Case B’
t
TR
CTM
DQA/B
t
TR
=0.5t
CYCLE
Case C
CTM
DQA/B
DQA/B
t
TR
=t
CYCLE
+t
DCW,MIN
Case D
t
TR
=t
CYCLE
+t
DCW,MIN
Case D’
CTM
DQA/B
DQA/B
t
TR
=t
CYCLE
Case E
t
TR
=t
CYCLE
Case E’
t
TR
t
TR
RD a1
Q(a1)
Q(a1)
Q(a1)
Q(a1)
t
CAC
-t
TR
t
CAC
-t
TR
-t
CYCLE
Q(a1)
Q(a1)
Q(a1)
Q(a1)
Q(a1)
t
CAC
-t
TR
t
CAC
-t
TR
+t
CYCLE
t
CAC
-t
TR
t
CAC
-t
TR
+t
CYCLE
t
CAC
-t
TR
t
CAC
-t
TR
-t
CYCLE
t
CAC
-t
TR
相關(guān)PDF資料
PDF描述
K4R881869M 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM
K4R881869M-NbCcG6 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM
K4R881869M-NCK7 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM
K4R881869M-NCK8 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM
K4S280432A 128Mbit SDRAM 8M x 4Bit x 4 Banks Synchronous DRAM LVTTL
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
K4R881869D 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:256/288Mbit RDRAM(D-die)
K4R881869D-FCM8 制造商:Samsung Electro-Mechanics 功能描述:16M X 18 DIRECT RAMBUS DRAM, PBGA92
K4R881869EFCT9 制造商:Samsung Semiconductor 功能描述:
K4R881869E-GCM8000 制造商:Samsung Semiconductor 功能描述:DRAM CHIP DIRECT RDRAM 288MBIT 2.5V 92PIN WBGA - Bulk
K4R881869E-GCM8T00 制造商:Samsung Semiconductor 功能描述:288MRDRAMDIRECT RDRAMX18WBGA - Tape and Reel
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