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參數(shù)資料
| 型號： | K4R881869M-NbCcG6 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| 中文描述： | 288Mbit RDRAM的為512k × 18位× 2 * 16屬銀行直接RDRAMTM |
| 文件頁數(shù)： | 61/64頁 |
| 文件大?。?/td> | 4084K |
| 代理商： | K4R881869M-NBCCG6 |
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Page 59
Direct RDRAM
K4R881869M
Rev. 0.9 Jan. 2000
Preliminary
Glossary of Terms
ACT
Activate command from AV field.
activate
To access a row and place in sense amp.
Two RDRAM banks which share sense
amps (also called doubled banks).
adjacent
ASYM
CCA register field for RSL V
OL
/V
OH
.
Power state - ready for ROW/COL
packets.
ATTN
ATTNR
Power state - transmitting Q packets.
Power state - receiving D packets.
ATTNW
AV
Opcode field in ROW packets.
A block of 2
RBIT
2
CBIT
storage cells in the
core of the RDRAM.
bank
BC
Bank address field in COLC packet.
CNFGA register field - # bank address
bits.
BBIT
broadcast
An operation executed by all RDRAMs.
Bank address field in ROW packets.
BR
bubble
Idle cycle(s) on RDRAM pins needed
because of a resource constraint.
CNFGB register field - 8/9 bits per byte.
BYT
BX
Bank address field in COLX packet.
Column address field in COLC packet.
C
CAL
Calibrate (I
OL
) command in XOP field.
CNFGB register field - # column address
bits.
CBIT
CCA
Control register - current control A.
Control register - current control B.
CCB
CFM,CFMN
Clock pins for receiving packets.
ROW/COL/DQ pins and external wires.
Channel
CLRR
Clear reset command from SOP field.
CMOS pin for initialization/power control.
CMD
CNFGA
Control register with configuration fields.
Control register with configuration fields.
CNFGB
COL
Pins for column-access control.
COLC,COLM,COLX packet on COL pins.
COL
COLC
Column operation packet on COL pins.
Write mask packet on COL pins.
COLM
column
Rows in a bank or activated row in sense
amps have 2
CBIT
dualocts column storage.
A decoded bit-combination from a field.
command
COLX
Extended operation packet on COL pins.
controller
A logic-device which drives the
ROW/COL /DQ wires for a Channel of
RDRAMs.
COP
Column opcode field in COLC packet.
The banks and sense amps of an RDRAM.
core
CTM,CTMN
Clock pins for transmitting packets.
current control
Periodic operations to update the proper
I
OL
value of RSL output drivers.
D
Write data packet on DQ pins.
CNFGB register field - doubled-bank.
DBL
DC
Device address field in COLC packet.
device
An RDRAM on a Channel.
Control register with device address that is
matched against DR, DC, and DX fields.
DEVID
DM
Device match for ROW packet decode.
doubled-bank
RDRAM with shared sense amp.
DQ
DQA and DQB pins.
Pins for data byte A.
DQA
DQB
Pins for data byte B.
NAPX register field - PDN/NAP exit.
DQS
DR,DR4T,DR4F
Device address field and packet framing
fields in ROWA and ROWR packets.
16 bytes - the smallest addressable datum.
dualoct
DX
Device address field in COLX packet.
A collection of bits in a packet.
field
INIT
Control register with initialization fields.
Configuring a Channel of RDRAMs so
they are ready to respond to transactions.
initialization
LSR
CNFGA register field - low-power self-
refresh.
Mask opcode field (COLM/COLX packet).
M
MA
Field in COLM packet for masking byte A.
Field in COLM packet for masking byte B.
MB
MSK
Mask command in M field.
Control register - manufacturer ID.
MVER
NAP
Power state - needs SCK/CMD wakeup.
Nap command in ROP field.
NAPR
NAPRC
Conditional nap command in ROP field.
NAPX register field - NAP exit delay A.
NAPXA
NAPXB
NAPX register field - NAP exit delay B.
No-operation command in COP field.
NOCOP
NOROP
No-operation command in ROP field.
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| K4R881869M-NCK7 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM |
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