參數(shù)資料
型號(hào)： K4R881869M-NCK7
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM
中文描述： 288Mbit RDRAM的為512k × 18位× 2 * 16屬銀行直接RDRAMTM
文件頁(yè)數(shù)： 25/64頁(yè)
文件大?。?/td> 4084K
代理商： K4R881869M-NCK7
Page 23
Direct RDRAM
K4R881869M
Rev. 0.9 Jan. 2000
Preliminary
Write/Retire Examples - continued
The RD will prevent a retire of the first WR from automati-
cally happening. But the first dualoct D(a1) in the write
buffer will be overwritten by the second WR dualoct D(b1)
if the RD command is issued in the third COLC packet.
Therefore, it is required in this situation that the controller
issue a NOCOP command in the third COLC packet,
delaying the RD command by a time of t
PACKET
. This situa-
tion is explicitly shown in Table 12 for the cases in which
t
CCDELAY
is equal to t
RTR
.
Figure 19 shows a possible result when a retire is held off for
a long time (an extended version of Figure 18-left). After a
WR command, a series of six RD commands are issued to
the same device (but to any combination of bank and column
addresses). In the meantime, the bank Ba to which the WR
command was originally directed is precharged, and a
different row Rc is activated. When the retire is automati-
cally performed, it is made to this new row, since the write
buffer only contains the bank and column address, not the
row address. The controller can insure that this doesn’t
happen by never precharging a bank with an unretired write
buffer. Note that in a system with more than one RDRAM,
there will never be more than two RDRAMs with unretired
write buffers. This is because a WR command issued to one
device automatically retires the write buffers of all other
devices written a time t
RTR
before or earlier.
Figure 18: Retire Held Off by Read (left) and Controller Forces WWR Gap (right)
CTM/CFM
DQA8..0
DQB8..0
COL4
..COL0
ROW2
..ROW0
T
0
T
4
T
8
T
12
T
1
T
5
T
9
T
13
T
2
T
6
T
10
T
14
T
3
T
7
T
11
T
15
T
16
T
20
T
17
T
21
T
18
T
22
T
19
T
23
Transaction a: WR
Transaction b: RD
a1= {Da,Ba,Ca1}
b1= {Da,Bb,Cb1}
Transaction a: WR
Transaction b: WR
Transaction c: RD
a1= {Da,Ba,Ca1}
b1= {Da,Bb,Cb1}
c1= {Da,Bc,Cc1}
D (a1)
WR a1
retire (a1)
MSK (a1)
RD b1
Q (b1)
DQB8..0
t
CWD
t
CAC
CTM/CFM
COL4
..COL0
ROW2
..ROW0
T
0
T
4
T
8
T
12
T
1
T
5
T
9
T
13
T
2
T
6
T
10
T
14
T
3
T
7
T
11
T
15
T
16
T
20
T
17
T
18
T
19
D (a1)
WR a1
RD c1
t
RTR
retire (a1)
MSK (a1)
t
CWD
t
CAC
WR b1
D (b1)
The controller must insert a NOCOP to retire (a1)
to make room for the data (b1) in the write buffer
The retire operation for a write can be
held off by a read to the same device
t
RTR
+ t
PACKET
Figure 19: Retire Held Off by Reads to Same Device, Write Buffer Retired to New Row
CTM/CFM
DQA8..0
DQB8..0
COL4
..COL0
ROW2
..ROW0
T
0
T
4
T
8
T
12
T
1
T
5
T
9
T
13
T
2
T
6
T
10
T
14
T
3
T
7
T
11
T
15
T
16
T
20
T
24
T
28
T
17
T
21
T
25
T
29
T
18
T
22
T
26
T
30
T
19
T
23
T
27
T
31
T
32
T
36
T
40
T
44
T
33
T
37
T
41
T
45
T
34
T
38
T
42
T
46
T
35
T
39
T
43
T
47
MSK (a1)
retire (a1)
RD b1
WR a1
PRER a2
t
RCD
ACT c0
t
RAS
t
RC
t
RP
ACT a0
t
CWD
t
RTR
Transaction a: WR
Transaction b: RD
a0 = {Da,Ba,Ra}
b1 = {Da,Bb,Cb1}
b4 = {Da,Bb,Cb4}
c0 = {Da,Ba,Rc}
a1 = {Da,Ba,Ca1}
b2 = {Da,Bb,Cb2}
b5 = {Da,Bb,Cb5}
a2 = {Da,Ba}
b3= {Da,Bb,Cb3}
b6 = {Da,Bb,Cb6}
RD b2
RD b3
RD b4
RD b5
RD b6
Q (b1)
t
CAC
Q (b2)
Q (b3)
Q (b4)
Q (b5)
Transaction c: WR
D (a1)
The retire operation puts the
write data in the new row
WARNING
This sequence is hazardous
and must be used with caution
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