參數(shù)資料
型號(hào)： K4R881869M-NCK7
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM
中文描述： 288Mbit RDRAM的為512k × 18位× 2 * 16屬銀行直接RDRAMTM
文件頁(yè)數(shù)： 46/64頁(yè)
文件大?。?/td> 4084K
代理商： K4R881869M-NCK7
Page 44
Direct RDRAM
K4R881869M
Rev. 0.9 Jan. 2000
Preliminary
Electrical Conditions
Timing Conditions
Table 18: Electrical Conditions
Symbol
Parameter and Conditions
Min
Max
Unit
T
J
Junction temperature under bias
-
100
°
C
V
DD,
V
DDA
Supply voltage
2.50 - 0.13
2.50 + 0.13
V
V
DD,N,
V
DDA,N
Supply voltage droop (DC) during NAP interval (t
NLIMIT
)
-
2.0
%
v
DD,N,
v
DDA,N
Supply voltage ripple (AC) during NAP interval (t
NLIMIT
)
-2.0
2.0
%
V
CMOS
Supply voltage for CMOS pins (2.5V controllers)
Supply voltage for CMOS pins (1.8V controllers)
2.50 - 0.13
1.80 - 0.1
2.50 + 0.25
1.80 + 0.2
V
V
V
TERM
Termination voltage
1.80 - 0.1
1.80 + 0.1
V
V
REF
Reference voltage
1.40 - 0.2
1.40 + 0.2
V
V
DIL
RSL data input - low voltage
V
REF
- 0.5
V
REF
- 0.2
V
V
DIH
RSL data input - high voltage
V
REF
+ 0.2
V
REF
+ 0.5
V
V
DIS
RSL data input swing: V
DIS
= V
DIH
- V
DIL
0.4
1.0
V
A
DI
RSL data asymmetry: A
DI
= [(V
DIH
- V
REF
) + (V
DIL
- V
REF
)]/V
DIS
0
-20
%
V
X
RSL clock input - crossing point of true and complement signals
1.3
1.8
V
V
CM
RSL clock input - common mode V
CM
= (V
CIH
+V
CIL)
/2
1.4
1.7
V
V
CIS,CTM
RSL clock input swing: V
CIS
= V
CIH
- V
CIL
(CTM,CTMN pins).
0.35
0.70
V
V
CIS,CFM
RSL clock input swing: V
CIS
= V
CIH
- V
CIL
(CFM,CFMN pins).
0.125
0.70
V
V
IL,CMOS
CMOS input low voltage
- 0.3
V
CMOS
/2 - 0.25
V
V
IH,CMOS
CMOS input high voltage
V
CMOS
/2 + 0.25
V
CMOS
+0.3
V
Table 19: Timing Conditions
Symbol
Parameter
Min
Max
Unit
Figure(s)
t
CYCLE
CTM and CFM cycle times (-600)
CTM and CFM cycle times (-711)
CTM and CFM cycle times (-800)
3.33
2.80
2.50
3.83
3.83
3.83
ns
ns
ns
Figure 53
Figure 53
Figure 53
t
CR
, t
CF
CTM and CFM input rise and fall times
0.2
0.5
ns
Figure 53
t
CH
, t
CL
CTM and CFM high and low times
40%
60%
t
CYCLE
Figure 53
t
TR
CTM-CFM differential (MSE/MS=0/0)
CTM-CFM differential (MSE/MS=1/1)
a
0.0
0.9
1.0
1.0
t
CYCLE
Figure 42
Figure 53
t
DCW
Domain crossing window
-0.1
0.1
t
CYCLE
Figure 59
t
DR
, t
DF
DQA/DQB/ROW/COL input rise/fall times
0.2
0.65
ns
Figure 54
t
S
, t
H
DQA/DQB/ROW/COL-to-CFM set/hold @ t
CYCLE
=3.33ns
DQA/DQB/ROW/COL-to-CFM set/hold @ t
CYCLE
=2.81ns
DQA/DQB/ROW/COL-to-CFM set/hold @ t
CYCLE
=2.50ns
0.275
b,d
0.240
c,d
0.200
d
-
-
-
ns
ns
ns
Figure 54
Figure 54
Figure 54
t
DR1,
t
DF1
SIO0, SIO1 input rise and fall times
-
5.0
ns
Figure 56
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