參數(shù)資料
型號(hào)： K4R881869M-NCK7
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM
中文描述： 288Mbit RDRAM的為512k × 18位× 2 * 16屬銀行直接RDRAMTM
文件頁(yè)數(shù)： 52/64頁(yè)
文件大?。?/td> 4084K
代理商： K4R881869M-NCK7
Page 50
Direct RDRAM
K4R881869M
Rev. 0.9 Jan. 2000
Preliminary
CMOS - Receive Timing
Figure 56 is a timing diagram which shows the detailed
requirements for the CMOS input signals .
The CMD and SIO0 signals are inputs which receive infor-
mation transmitted by a controller (or by another RDRAM’s
SIO1 output. SCK is the CMOS clock signal driven by the
controller. All signals are high true.
The cycle time, high phase time, and low phase time of the
SCK clock are t
CYCLE1
, t
CH1
and t
CL1
, all measured at the
50% level. The rise and fall times of SCK, CMD, and SIO0
are t
DR1
and t
DF1
, measured at the 20% and 80% levels.
The CMD signal is sampled twice per t
CYCLE1
interval, on
the rising edge (odd data) and the falling edge (even data).
The set/hold window of the sample points is t
S1
/t
H1.
The
SCK and CMD timing points are measured at the 50% level.
The SIO0 signal is sampled once per t
CYCLE1
interval on the
falling edge. The set/hold window of the sample points is
t
S2
/t
H2.
The SCK and SIO0 timing points are measured at the
50% level.
Figure 56: CMOS Timing - Data Signals for Receive
V
IH,CMOS
50%
V
IL,CMOS
80%
20%
SCK
t
S1
CMD
t
DR2
t
H1
t
S1
t
H1
even
odd
t
DF2
V
IH,CMOS
50%
V
IL,CMOS
80%
20%
t
DR2
t
DF2
t
CH1
t
CL1
t
CYCLE1
t
S2
SIO0
t
DR1
t
H2
t
DF1
V
IH,CMOS
50%
V
IL,CMOS
80%
20%
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