參數(shù)資料
型號(hào)： K4R881869M-NCK7
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM
中文描述： 288Mbit RDRAM的為512k × 18位× 2 * 16屬銀行直接RDRAMTM
文件頁數(shù)： 62/64頁
文件大?。?/td> 4084K
代理商： K4R881869M-NCK7
Page 60
Direct RDRAM
K4R881869M
Rev. 0.9 Jan. 2000
Preliminary
NOXOP
No-operation command in XOP field.
INIT register field- NAP self-refresh.
NSR
packet
A collection of bits carried on the Channel.
Power state - needs SCK/CMD wakeup.
PDN
PDNR
Powerdown command in ROP field.
Control register - PDN exit delay A.
PDNXA
PDNXB
Control register - PDN exit delay B.
pin efficiency
The fraction of non-idle cycles on a pin.
PRE
PREC,PRER,PREX precharge commands.
Precharge command in COP field.
PREC
precharge
Prepares sense amp and bank for activate.
Precharge command in ROP field.
PRER
PREX
Precharge command in XOP field.
INIT register field - PDN/NAP exit.
PSX
PSR
INIT register field - PDN self-refresh.
CNFGB register field - protocol version.
PVER
Q
Read data packet on DQ pins.
Row address field of ROWA packet.
R
RBIT
CNFGB register field - # row address bits.
Read (/precharge) command in COP field.
RD/RDA
read
Operation of accesssing sense amp data.
Moving information from the Channel into
the RDRAM (a serial stream is demuxed).
receive
REFA
Refresh-activate command in ROP field.
Control register - next bank (self-refresh).
REFB
REFBIT
CNFGA register field - ignore bank bits
(for REFA and self-refresh).
Refresh-precharge command in ROP field.
REFP
REFR
Control register - next row for REFA.
Periodic operations to restore storage cells.
refresh
retire
The automatic operation that stores write
buffer into sense amp after WR command.
RLXC,RLXR,RLXX relax commands.
RLX
RLXC
Relax command in COP field.
Relax command in ROP field.
RLXR
RLXX
Relax command in XOP field.
Row-opcode field in ROWR packet.
2
CBIT
dualocts of cells (bank/sense amp).
Pins for row-access control
ROP
row
ROW
ROW
ROWA or ROWR packets on ROW pins.
Activate packet on ROW pins.
ROWA
ROWR
Row operation packet on ROW pins.
Alternate name for ROW/COL pins.
RQ
RSL
Rambus Signaling Levels.
Sample (I
OL
) command in XOP field.
Serial address packet for control register
transactions w/ SA address field.
Serial broadcast field in SRQ.
SAM
SA
SBC
SCK
CMOS clock pin..
Serial data packet for control register
transactions w/ SD data field.
SD
SDEV
Serial device address in SRQ packet.
INIT register field - Serial device ID.
SDEVID
self-refresh
Refresh mode for PDN and NAP.
Fast storage that holds copy of bank’s row.
sense amp
SETF
Set fast clock command from SOP field.
Set reset command from SOP field.
SETR
SINT
Serial interval packet for control register
read/write transactions.
CMOS serial pins for control registers.
SIO0,SIO1
SOP
Serial opcode field in SRQ.
Serial read opcode command from SOP.
SRD
SRP
INIT register field - Serial repeat bit.
Serial request packet for control register
read/write transactions.
SRQ
STBY
Power state - ready for ROW packets.
Control register - stepping version.
SVER
SWR
Serial write opcode command from SOP.
TCLSCAS register field - t
CAS
core delay.
TCLSCAS register field - t
CLS
core delay.
Control register - t
CAS
and t
CLS
delays.
Control register - t
CYCLE
delay.
Control register - t
DAC
delay.
Control register - for test purposes.
Control register - for test purposes.
TCAS
TCLS
TCLSCAS
TCYCLE
TDAC
TEST77
TEST78
TRDLY
Control register - t
RDLY
delay.
ROW,COL,DQ packets for memory
access.
transaction
transmit
Moving information from the RDRAM
onto the Channel (parallel word is muxed).
Write (/precharge) command in COP field.
WR/WRA
write
Operation of modifying sense amp data.
Extended opcode field in COLX packet.
XOP
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參數(shù)描述
K4R881869M-NCK8 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM
K4R881869M-NCK8000 制造商:Samsung SDI 功能描述:
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K4S160822DT-G/F10 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:2Mx8 SDRAM 1M x 8bit x 2 Banks Synchronous DRAM LVTTL
K4S160822DT-G/F7 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:2Mx8 SDRAM 1M x 8bit x 2 Banks Synchronous DRAM LVTTL
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