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參數(shù)資料
| 型號(hào)： | K4R881869M-NCK8 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| 中文描述： | 288Mbit RDRAM的為512k × 18位× 2 * 16屬銀行直接RDRAMTM |
| 文件頁數(shù)： | 53/64頁 |
| 文件大?。?/td> | 4084K |
| 代理商： | K4R881869M-NCK8 |
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Page 51
Direct RDRAM
K4R881869M
Rev. 0.9 Jan. 2000
Preliminary
The SCK clock is also used for sampling data on RSL inputs
in one situation. Figure 48 shows the PDN and NAP exit
sequences. If the PSX field of the INIT register is one (see
Figure 27), then the PDN and NAP exit sequences are broad-
cast; i.e. all RDRAMs that are in PDN or NAP will perform
the exit sequence. If the PSX field of the INIT register is
zero, then the PDN and NAP exit sequences are directed; i.e.
only one RDRAM that is in PDN or NAP will perform the
exit sequence.
The address of that RDRAM is specified on the DQA[5:0]
bus in the set hold window t
S3
/t
H3
around the rising edge of
SCK. This is shown in Figure 57. The SCK timing point is
measured at the 50% level, and the DQA[5:0] bus signals are
measured at the V
REF
level.
Figure 57: CMOS Timing - Device Address for NAP or PDN Exit
V
IH,CMOS
50%
V
IL,CMOS
80%
20%
SCK
V
DIH
V
REF
V
DIL
80%
20%
DQA[5:0]
t
S3
t
H3
PDEV
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