參數(shù)資料
型號: K4R881869M
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM
中文描述: 288Mbit RDRAM的為512k × 18位× 2 * 16屬銀行直接RDRAMTM
文件頁數(shù): 50/64頁
文件大?。?/td> 4084K
代理商: K4R881869M
Page 48
Direct RDRAM
K4R881869M
Rev. 0.9 Jan. 2000
Preliminary
RSL - Receive Timing
Figure 54 is a timing diagram which shows the detailed
requirements for the RSL input signals on the Channel.
The DQA, DQB, ROW, and COL signals are inputs which
receive information transmitted by a Direct RAC on the
Channel. Each signal is sampled twice per t
CYCLE
interval.
The set/hold window of the sample points is t
S
/t
H.
The
sample points are centered at the 0% and 50% points of a
cycle, measured relative to the crossing points of the falling
CFM clock edge. The set and hold parameters are measured
at the V
REF
voltage point of the input transition.
The t
DR
and t
DF
rise- and fall-time parameters are measured
at the 20% and 80% points of the input transition.
Figure 54: RSL Timing - Data Signals for Receive
V
DIH
V
REF
V
DIL
80%
20%
V
CIH
50%
V
CIL
80%
20%
CFM
CFMN
DQA
t
S
ROW
DQB
t
DF
t
DR
t
H
t
S
t
H
0.5t
CYCLE
even
odd
COL
V
CM
V
X+
V
X-
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