- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374277 > K4R881869M (SAMSUNG SEMICONDUCTOR CO. LTD.) 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM PDF資料下載
參數(shù)資料
| 型號： | K4R881869M |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| 中文描述： | 288Mbit RDRAM的為512k × 18位× 2 * 16屬銀行直接RDRAMTM |
| 文件頁數(shù)： | 52/64頁 |
| 文件大?。?/td> | 4084K |
| 代理商： | K4R881869M |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁當(dāng)前第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
Page 50
Direct RDRAM
K4R881869M
Rev. 0.9 Jan. 2000
Preliminary
CMOS - Receive Timing
Figure 56 is a timing diagram which shows the detailed
requirements for the CMOS input signals .
The CMD and SIO0 signals are inputs which receive infor-
mation transmitted by a controller (or by another RDRAM’s
SIO1 output. SCK is the CMOS clock signal driven by the
controller. All signals are high true.
The cycle time, high phase time, and low phase time of the
SCK clock are t
CYCLE1
, t
CH1
and t
CL1
, all measured at the
50% level. The rise and fall times of SCK, CMD, and SIO0
are t
DR1
and t
DF1
, measured at the 20% and 80% levels.
The CMD signal is sampled twice per t
CYCLE1
interval, on
the rising edge (odd data) and the falling edge (even data).
The set/hold window of the sample points is t
S1
/t
H1.
The
SCK and CMD timing points are measured at the 50% level.
The SIO0 signal is sampled once per t
CYCLE1
interval on the
falling edge. The set/hold window of the sample points is
t
S2
/t
H2.
The SCK and SIO0 timing points are measured at the
50% level.
Figure 56: CMOS Timing - Data Signals for Receive
V
IH,CMOS
50%
V
IL,CMOS
80%
20%
SCK
t
S1
CMD
t
DR2
t
H1
t
S1
t
H1
even
odd
t
DF2
V
IH,CMOS
50%
V
IL,CMOS
80%
20%
t
DR2
t
DF2
t
CH1
t
CL1
t
CYCLE1
t
S2
SIO0
t
DR1
t
H2
t
DF1
V
IH,CMOS
50%
V
IL,CMOS
80%
20%
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K4R881869M-NbCcG6 | 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| K4R881869M-NCK7 | 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| K4R881869M-NCK8 | 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| K4S280432A | 128Mbit SDRAM 8M x 4Bit x 4 Banks Synchronous DRAM LVTTL |
| K4S280432C | 128Mbit SDRAM 8M x 4Bit x 4 Banks Synchronous DRAM LVTTL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K4R881869M-NBCCG6 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| K4R881869M-NCK7 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| K4R881869M-NCK8 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| K4R881869M-NCK8000 | 制造商:Samsung SDI 功能描述: |
| K4S160822D | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:2Mx8 SDRAM 1M x 8bit x 2 Banks Synchronous DRAM LVTTL |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。